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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (C) 2023 PHYTEC Messtechnik GmbH * Author: Christoph Stoidner <c.stoidner@phytec.de> * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com> * Copyright (C) 2024 PHYTEC Messtechnik GmbH */ #include <asm/arch/clock.h> #include <asm/arch/ddr.h> #include <asm/arch/mu.h> #include <asm/arch/sys_proto.h> #include <asm/arch/trdc.h> #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/ele_api.h> #include <asm/sections.h> #include <init.h> #include <power/pmic.h> #include <power/pca9450.h> #include <spl.h> #include "../common/imx93_som_detection.h" DECLARE_GLOBAL_DATA_PTR; #define EEPROM_ADDR 0x50 /* * Prototypes of automatically generated ram config file */ void set_dram_timings_2gb_lpddr4x(void); void set_dram_timings_1gb_lpddr4x_900mhz(void); int spl_board_boot_device(enum boot_device boot_dev_spl) { return BOOT_DEVICE_BOOTROM; } void spl_board_init(void) { int ret; ret = ele_start_rng(); if (ret) printf("Fail to start RNG: %d\n", ret); puts("Normal Boot\n"); } void spl_dram_init(void) { int ret; enum phytec_imx93_ddr_eeprom_code ddr_opt = PHYTEC_IMX93_DDR_INVALID; ret = phytec_eeprom_data_setup(NULL, CONFIG_PHYTEC_EEPROM_BUS, EEPROM_ADDR); if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX)) goto out; ret = phytec_imx93_detect(NULL); if (!ret) phytec_print_som_info(NULL); if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX)) { if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB)) ddr_opt = PHYTEC_IMX93_LPDDR4X_1GB; else if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_LPDDR4X_2GB)) ddr_opt = PHYTEC_IMX93_LPDDR4X_2GB; } else { ddr_opt = phytec_imx93_get_opt(NULL, PHYTEC_IMX93_OPT_DDR); } switch (ddr_opt) { case PHYTEC_IMX93_LPDDR4X_1GB: if (is_voltage_mode(VOLT_LOW_DRIVE)) set_dram_timings_1gb_lpddr4x_900mhz(); break; case PHYTEC_IMX93_LPDDR4X_2GB: set_dram_timings_2gb_lpddr4x(); break; default: goto out; } ddr_init(&dram_timing); return; out: puts("Could not detect correct RAM type and size. Fall back to default.\n"); if (is_voltage_mode(VOLT_LOW_DRIVE)) set_dram_timings_1gb_lpddr4x_900mhz(); ddr_init(&dram_timing); } int power_init_board(void) { struct udevice *dev; int ret; unsigned int val = 0, buck_val; ret = pmic_get("pmic@25", &dev); if (ret == -ENODEV) { puts("No pca9450@25\n"); return 0; } if (ret != 0) return ret; /* BUCKxOUT_DVS0/1 control BUCK123 output */ pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); /* enable DVS control through PMIC_STBY_REQ */ pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); ret = pmic_reg_read(dev, PCA9450_PWR_CTRL); if (ret < 0) return ret; val = ret; if (is_voltage_mode(VOLT_LOW_DRIVE)) { buck_val = 0x0c; /* 0.8v for Low drive mode */ printf("PMIC: Low Drive Voltage Mode\n"); } else if (is_voltage_mode(VOLT_NOMINAL_DRIVE)) { buck_val = 0x10; /* 0.85v for Nominal drive mode */ printf("PMIC: Nominal Voltage Mode\n"); } else { buck_val = 0x14; /* 0.9v for Over drive mode */ printf("PMIC: Over Drive Voltage Mode\n"); } if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) { pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val); pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val); } else { pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val + 0x4); pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val + 0x4); } /* set standby voltage to 0.65v */ if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0); else pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4); /* I2C_LT_EN*/ pmic_reg_write(dev, 0xa, 0x3); return 0; } void board_init_f(ulong dummy) { int ret; /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); timer_init(); arch_cpu_init(); spl_early_init(); preloader_console_init(); ret = imx9_probe_mu(); if (ret) { printf("Fail to init ELE API\n"); } else { debug("SOC: 0x%x\n", gd->arch.soc_rev); debug("LC: 0x%x\n", gd->arch.lifecycle); } clock_init_late(); power_init_board(); if (!is_voltage_mode(VOLT_LOW_DRIVE)) set_arm_core_max_clk(); /* Init power of mix */ soc_power_init(); /* Setup TRDC for DDR access */ trdc_init(); /* DDR initialization */ spl_dram_init(); /* Put M33 into CPUWAIT for following kick */ ret = m33_prepare(); if (!ret) printf("M33 prepare ok\n"); board_init_r(NULL, 0); } |