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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 | // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2018 NXP */ #include <errno.h> #include <log.h> #include <asm/io.h> #include <asm/arch/ddr.h> #include <asm/arch/clock.h> #include <asm/arch/ddr.h> #include <asm/arch/sys_proto.h> static inline void poll_pmu_message_ready(void) { unsigned int reg; do { reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0004)); } while (reg & 0x1); } static inline void ack_pmu_message_receive(void) { unsigned int reg; reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0031), 0x0); do { reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0004)); } while (!(reg & 0x1)); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0031), 0x1); } static inline unsigned int get_mail(void) { unsigned int reg; poll_pmu_message_ready(); reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0032)); ack_pmu_message_receive(); return reg; } static inline unsigned int get_stream_message(void) { unsigned int reg, reg2; poll_pmu_message_ready(); reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0032)); reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0034)); reg2 = (reg2 << 16) | reg; ack_pmu_message_receive(); return reg2; } static inline void decode_major_message(unsigned int mail) { debug("[PMU Major message = 0x%08x]\n", mail); } static inline void decode_streaming_message(void) { unsigned int string_index, arg __maybe_unused; int i = 0; string_index = get_stream_message(); debug("PMU String index = 0x%08x\n", string_index); while (i < (string_index & 0xffff)) { arg = get_stream_message(); debug("arg[%d] = 0x%08x\n", i, arg); i++; } debug("\n"); } int wait_ddrphy_training_complete(void) { unsigned int mail; while (1) { mail = get_mail(); decode_major_message(mail); if (mail == 0x08) { decode_streaming_message(); } else if (mail == 0x07) { debug("Training PASS\n"); return 0; } else if (mail == 0xff) { printf("Training FAILED\n"); return -1; } } } void ddrphy_init_set_dfi_clk(unsigned int drate) { switch (drate) { case 4000: dram_pll_init(MHZ(1000)); dram_disable_bypass(); break; case 3734: case 3733: case 3732: dram_pll_init(MHZ(933)); dram_disable_bypass(); break; case 3600: dram_pll_init(MHZ(900)); dram_disable_bypass(); break; case 3200: dram_pll_init(MHZ(800)); dram_disable_bypass(); break; case 3000: dram_pll_init(MHZ(750)); dram_disable_bypass(); break; case 2800: dram_pll_init(MHZ(700)); dram_disable_bypass(); break; case 2400: dram_pll_init(MHZ(600)); dram_disable_bypass(); break; case 1866: dram_pll_init(MHZ(466)); dram_disable_bypass(); break; case 1600: dram_pll_init(MHZ(400)); dram_disable_bypass(); break; case 1200: dram_pll_init(MHZ(300)); dram_disable_bypass(); break; case 1066: dram_pll_init(MHZ(266)); dram_disable_bypass(); break; case 933: dram_pll_init(MHZ(233)); dram_disable_bypass(); break; case 800: dram_pll_init(MHZ(200)); dram_disable_bypass(); break; case 667: dram_pll_init(MHZ(167)); dram_disable_bypass(); break; case 625: dram_enable_bypass(MHZ(625)); break; case 400: dram_enable_bypass(MHZ(400)); break; case 333: dram_enable_bypass(MHZ(333)); break; case 200: dram_enable_bypass(MHZ(200)); break; case 100: dram_enable_bypass(MHZ(100)); break; default: return; } } void ddrphy_init_read_msg_block(enum fw_type type) { } |