U-Boot

// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright 2025 Cix Technology Group Co., Ltd.
 *
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/cix,sky1.h>

/ {
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a520";
			enable-method = "psci";
			reg = <0x0 0x0>;
			device_type = "cpu";
			capacity-dmips-mhz = <403>;
		};

		cpu1: cpu@100 {
			compatible = "arm,cortex-a520";
			enable-method = "psci";
			reg = <0x0 0x100>;
			device_type = "cpu";
			capacity-dmips-mhz = <403>;
		};

		cpu2: cpu@200 {
			compatible = "arm,cortex-a520";
			enable-method = "psci";
			reg = <0x0 0x200>;
			device_type = "cpu";
			capacity-dmips-mhz = <403>;
		};

		cpu3: cpu@300 {
			compatible = "arm,cortex-a520";
			enable-method = "psci";
			reg = <0x0 0x300>;
			device_type = "cpu";
			capacity-dmips-mhz = <403>;
		};

		cpu4: cpu@400 {
			compatible = "arm,cortex-a720";
			enable-method = "psci";
			reg = <0x0 0x400>;
			device_type = "cpu";
			capacity-dmips-mhz = <1024>;
		};

		cpu5: cpu@500 {
			compatible = "arm,cortex-a720";
			enable-method = "psci";
			reg = <0x0 0x500>;
			device_type = "cpu";
			capacity-dmips-mhz = <1024>;
		};

		cpu6: cpu@600 {
			compatible = "arm,cortex-a720";
			enable-method = "psci";
			reg = <0x0 0x600>;
			device_type = "cpu";
			capacity-dmips-mhz = <1024>;
		};

		cpu7: cpu@700 {
			compatible = "arm,cortex-a720";
			enable-method = "psci";
			reg = <0x0 0x700>;
			device_type = "cpu";
			capacity-dmips-mhz = <1024>;
		};

		cpu8: cpu@800 {
			compatible = "arm,cortex-a720";
			enable-method = "psci";
			reg = <0x0 0x800>;
			device_type = "cpu";
			capacity-dmips-mhz = <1024>;
		};

		cpu9: cpu@900 {
			compatible = "arm,cortex-a720";
			enable-method = "psci";
			reg = <0x0 0x900>;
			device_type = "cpu";
			capacity-dmips-mhz = <1024>;
		};

		cpu10: cpu@a00 {
			compatible = "arm,cortex-a720";
			enable-method = "psci";
			reg = <0x0 0xa00>;
			device_type = "cpu";
			capacity-dmips-mhz = <1024>;
		};

		cpu11: cpu@b00 {
			compatible = "arm,cortex-a720";
			enable-method = "psci";
			reg = <0x0 0xb00>;
			device_type = "cpu";
			capacity-dmips-mhz = <1024>;
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
				core4 {
					cpu = <&cpu4>;
				};
				core5 {
					cpu = <&cpu5>;
				};
				core6 {
					cpu = <&cpu6>;
				};
				core7 {
					cpu = <&cpu7>;
				};
				core8 {
					cpu = <&cpu8>;
				};
				core9 {
					cpu = <&cpu9>;
				};
				core10 {
					cpu = <&cpu10>;
				};
				core11 {
					cpu = <&cpu11>;
				};
			};
		};
	};

	firmware {
		ap_to_pm_scmi: scmi {
			compatible = "arm,scmi";
			mbox-names = "tx", "rx";
			mboxes = <&mbox_ap2pm 8>, <&mbox_pm2ap 8>;
			shmem = <&ap2pm_scmi_mem>, <&pm2ap_scmi_mem>;
			#address-cells = <1>;
			#size-cells = <0>;

			scmi_clk: protocol@14 {
				reg = <0x14>;
				#clock-cells = <1>;
			};
		};
	};

	pmu-a520 {
		compatible = "arm,cortex-a520-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition0>;
	};

	pmu-a720 {
		compatible = "arm,cortex-a720-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition1>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	soc@0 {
		compatible = "simple-bus";
		ranges = <0 0 0 0 0x20 0>;
		dma-ranges;
		#address-cells = <2>;
		#size-cells = <2>;

		i2c0: i2c@4010000 {
			compatible = "cdns,i2c-r1p14";
			reg = <0x0 0x04010000 0x0 0x10000>;
			clock-frequency = <400000>;
			clocks = <&scmi_clk CLK_TREE_FCH_I2C0_APB>;
			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH 0>;
			status = "disabled";
		};

		i2c1: i2c@4020000 {
			compatible = "cdns,i2c-r1p14";
			reg = <0x0 0x04020000 0x0 0x10000>;
			clock-frequency = <400000>;
			clocks = <&scmi_clk CLK_TREE_FCH_I2C1_APB>;
			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH 0>;
			status = "disabled";
		};

		i2c2: i2c@4030000 {
			compatible = "cdns,i2c-r1p14";
			reg = <0x0 0x04030000 0x0 0x10000>;
			clock-frequency = <400000>;
			clocks = <&scmi_clk CLK_TREE_FCH_I2C2_APB>;
			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH 0>;
			status = "disabled";
		};

		i2c3: i2c@4040000 {
			compatible = "cdns,i2c-r1p14";
			reg = <0x0 0x04040000 0x0 0x10000>;
			clock-frequency = <400000>;
			clocks = <&scmi_clk CLK_TREE_FCH_I2C3_APB>;
			interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>;
			status = "disabled";
		};

		i2c4: i2c@4050000 {
			compatible = "cdns,i2c-r1p14";
			reg = <0x0 0x04050000 0x0 0x10000>;
			clock-frequency = <400000>;
			clocks = <&scmi_clk CLK_TREE_FCH_I2C4_APB>;
			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH 0>;
			status = "disabled";
		};

		i2c5: i2c@4060000 {
			compatible = "cdns,i2c-r1p14";
			reg = <0x0 0x04060000 0x0 0x10000>;
			clock-frequency = <400000>;
			clocks = <&scmi_clk CLK_TREE_FCH_I2C5_APB>;
			interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH 0>;
			status = "disabled";
		};

		i2c6: i2c@4070000 {
			compatible = "cdns,i2c-r1p14";
			reg = <0x0 0x04070000 0x0 0x10000>;
			clock-frequency = <400000>;
			clocks = <&scmi_clk CLK_TREE_FCH_I2C6_APB>;
			interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH 0>;
			status = "disabled";
		};

		i2c7: i2c@4080000 {
			compatible = "cdns,i2c-r1p14";
			reg = <0x0 0x04080000 0x0 0x10000>;
			clock-frequency = <400000>;
			clocks = <&scmi_clk CLK_TREE_FCH_I2C7_APB>;
			interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>;
			status = "disabled";
		};

		spi0: spi@4090000 {
			compatible = "cix,sky1-spi-r1p6", "cdns,spi-r1p6";
			reg = <0x0 0x04090000 0x0 0x10000>;
			clocks = <&scmi_clk CLK_TREE_FCH_SPI0_APB>,
				 <&scmi_clk CLK_TREE_FCH_SPI0_APB>;
			clock-names = "ref_clk", "pclk";
			interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>;
			status = "disabled";
		};

		spi1: spi@40a0000 {
			compatible = "cix,sky1-spi-r1p6", "cdns,spi-r1p6";
			reg = <0x0 0x040a0000 0x0 0x10000>;
			clocks = <&scmi_clk CLK_TREE_FCH_SPI1_APB>,
				 <&scmi_clk CLK_TREE_FCH_SPI1_APB>;
			clock-names = "ref_clk", "pclk";
			interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>;
			status = "disabled";
		};

		uart0: serial@40b0000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x0 0x040b0000 0x0 0x1000>;
			interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&scmi_clk CLK_TREE_FCH_UART0_FUNC>, <&scmi_clk CLK_TREE_FCH_UART0_APB>;
			clock-names = "uartclk", "apb_pclk";
			status = "disabled";
		};

		uart1: serial@40c0000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x0 0x040c0000 0x0 0x1000>;
			interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&scmi_clk CLK_TREE_FCH_UART1_FUNC>, <&scmi_clk CLK_TREE_FCH_UART1_APB>;
			clock-names = "uartclk", "apb_pclk";
			status = "disabled";
		};

		uart2: serial@40d0000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x0 0x040d0000 0x0 0x1000>;
			interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&scmi_clk CLK_TREE_FCH_UART2_FUNC>, <&scmi_clk CLK_TREE_FCH_UART2_APB>;
			clock-names = "uartclk", "apb_pclk";
			status = "disabled";
		};

		uart3: serial@40e0000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x0 0x040e0000 0x0 0x1000>;
			interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&scmi_clk CLK_TREE_FCH_UART3_FUNC>, <&scmi_clk CLK_TREE_FCH_UART3_APB>;
			clock-names = "uartclk", "apb_pclk";
			status = "disabled";
		};

		i3c0: i3c@40f0000 {
			compatible = "cdns,i3c-master";
			reg = <0x0 0x040f0000 0x0 0x10000>;
			#address-cells = <3>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&scmi_clk CLK_TREE_FCH_I3C0_APB>,
				 <&scmi_clk CLK_TREE_FCH_I3C0_FUNC>;
			clock-names = "pclk", "sysclk";
			i3c-scl-hz = <400000>;
			i2c-scl-hz = <100000>;
			status = "disabled";
		};

		i3c1: i3c@4100000 {
			compatible = "cdns,i3c-master";
			reg = <0x0 0x04100000 0x0 0x10000>;
			#address-cells = <3>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&scmi_clk CLK_TREE_FCH_I3C1_APB>,
				 <&scmi_clk CLK_TREE_FCH_I3C1_FUNC>;
			clock-names = "pclk", "sysclk";
			i3c-scl-hz = <400000>;
			i2c-scl-hz = <100000>;
			status = "disabled";
		};

		iomuxc: pinctrl@4170000 {
			compatible = "cix,sky1-pinctrl";
			reg = <0x0 0x04170000 0x0 0x1000>;
		};

		mbox_ap2se: mailbox@5060000 {
			compatible = "cix,sky1-mbox";
			reg = <0x0 0x05060000 0x0 0x10000>;
			interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH 0>;
			#mbox-cells = <1>;
			cix,mbox-dir = "tx";
		};

		mbox_se2ap: mailbox@5070000 {
			compatible = "cix,sky1-mbox";
			reg = <0x0 0x05070000 0x0 0x10000>;
			interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>;
			#mbox-cells = <1>;
			cix,mbox-dir = "rx";
		};

		ap2pm_scmi_mem: shmem@6590000 {
			compatible = "arm,scmi-shmem";
			reg = <0x0 0x06590000 0x0 0x80>;
			reg-io-width = <4>;
		};

		mbox_ap2pm: mailbox@6590080 {
			compatible = "cix,sky1-mbox";
			reg = <0x0 0x06590080 0x0 0xff80>;
			interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>;
			#mbox-cells = <1>;
			cix,mbox-dir = "tx";
		};

		pm2ap_scmi_mem: shmem@65a0000 {
			compatible = "arm,scmi-shmem";
			reg = <0x0 0x065a0000 0x0 0x80>;
			reg-io-width = <4>;
		};

		mbox_pm2ap: mailbox@65a0080 {
			compatible = "cix,sky1-mbox";
			reg = <0x0 0x065a0080 0x0 0xff80>;
			interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 0>;
			#mbox-cells = <1>;
			cix,mbox-dir = "rx";
		};

		mbox_sfh2ap: mailbox@8090000 {
			compatible = "cix,sky1-mbox";
			reg = <0x0 0x08090000 0x0 0x10000>;
			interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
			#mbox-cells = <1>;
			cix,mbox-dir = "rx";
		};

		mbox_ap2sfh: mailbox@80a0000 {
			compatible = "cix,sky1-mbox";
			reg = <0x0 0x080a0000 0x0 0x10000>;
			interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
			#mbox-cells = <1>;
			cix,mbox-dir = "tx";
		};

		pcie_x8_rc: pcie@a010000 {
			compatible = "cix,sky1-pcie-host";
			reg = <0x00 0x0a010000 0x00 0x10000>,
			      <0x00 0x2c000000 0x00 0x4000000>,
			      <0x00 0x0a000300 0x00 0x100>,
			      <0x00 0x0a000400 0x00 0x100>,
			      <0x00 0x60000000 0x00 0x00100000>;
			reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg";
			ranges = <0x01000000 0x0 0x60100000 0x0 0x60100000 0x0 0x00100000>,
				 <0x02000000 0x0 0x60200000 0x0 0x60200000 0x0 0x1fe00000>,
				 <0x43000000 0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>;
			#address-cells = <3>;
			#size-cells = <2>;
			bus-range = <0xc0 0xff>;
			device_type = "pci";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>,
					<0 0 0 2 &gic 0 0 GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>,
					<0 0 0 3 &gic 0 0 GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>,
					<0 0 0 4 &gic 0 0 GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH 0>;
			msi-map = <0xc000 &gic_its 0xc000 0x4000>;
			status = "disabled";
		};

		pcie_x4_rc: pcie@a070000 {
			compatible = "cix,sky1-pcie-host";
			reg = <0x00 0x0a070000 0x00 0x10000>,
			      <0x00 0x29000000 0x00 0x3000000>,
			      <0x00 0x0a060300 0x00 0x40>,
			      <0x00 0x0a060400 0x00 0x40>,
			      <0x00 0x50000000 0x00 0x00100000>;
			reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg";
			ranges = <0x01000000 0x00 0x50100000 0x00 0x50100000 0x00 0x00100000>,
				 <0x02000000 0x00 0x50200000 0x00 0x50200000 0x00 0x0fe00000>,
				 <0x43000000 0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>;
			#address-cells = <3>;
			#size-cells = <2>;
			bus-range = <0x90 0xbf>;
			device_type = "pci";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 0>,
					<0 0 0 2 &gic 0 0 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0>,
					<0 0 0 3 &gic 0 0 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0>,
					<0 0 0 4 &gic 0 0 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 0>;
			msi-map = <0x9000 &gic_its 0x9000 0x3000>;
			status = "disabled";
		};

		pcie_x2_rc: pcie@a0c0000 {
			compatible = "cix,sky1-pcie-host";
			reg = <0x00 0x0a0c0000 0x00 0x10000>,
			      <0x00 0x26000000 0x00 0x3000000>,
			      <0x00 0x0a0600340 0x00 0x20>,
			      <0x00 0x0a0600440 0x00 0x20>,
			      <0x00 0x40000000 0x00 0x00100000>;
			reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg";
			ranges = <0x01000000 0x0 0x40100000 0x0 0x40100000 0x0 0x00100000>,
				 <0x02000000 0x0 0x40200000 0x0 0x40200000 0x0 0x0fe00000>,
				 <0x43000000 0x10 0x00000000 0x10 0x00000000 0x04 0x00000000>;
			#address-cells = <3>;
			#size-cells = <2>;
			bus-range = <0x60 0x8f>;
			device_type = "pci";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 0>,
					<0 0 0 2 &gic 0 0 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 0>,
					<0 0 0 3 &gic 0 0 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 0>,
					<0 0 0 4 &gic 0 0 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 0>;
			msi-map = <0x6000 &gic_its 0x6000 0x3000>;
			status = "disabled";
		};

		pcie_x1_0_rc: pcie@a0d0000 {
			compatible = "cix,sky1-pcie-host";
			reg = <0x00 0x0a0d0000 0x00 0x10000>,
			      <0x00 0x20000000 0x00 0x3000000>,
			      <0x00 0x0a060360 0x00 0x20>,
			      <0x00 0x0a060460 0x00 0x20>,
			      <0x00 0x30000000 0x00 0x00100000>;
			reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg";
			ranges = <0x01000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000>,
				 <0x02000000 0x0 0x30200000 0x0 0x30200000 0x0 0x07e00000>,
				 <0x43000000 0x08 0x00000000 0x08 0x00000000 0x04 0x00000000>;
			#address-cells = <3>;
			#size-cells = <2>;
			bus-range = <0x00 0x2f>;
			device_type = "pci";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>,
					<0 0 0 2 &gic 0 0 GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH 0>,
					<0 0 0 3 &gic 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>,
					<0 0 0 4 &gic 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>;
			msi-map = <0x0000 &gic_its 0x0000 0x3000>;
			status = "disabled";
		};

		pcie_x1_1_rc: pcie@a0e0000 {
			compatible = "cix,sky1-pcie-host";
			reg = <0x00 0x0a0e0000 0x00 0x10000>,
			      <0x00 0x23000000 0x00 0x3000000>,
			      <0x00 0x0a060380 0x00 0x20>,
			      <0x00 0x0a060480 0x00 0x20>,
			      <0x00 0x38000000 0x00 0x00100000>;
			reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg";
			ranges = <0x01000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>,
				 <0x02000000 0x0 0x38200000 0x0 0x38200000 0x0 0x07e00000>,
				 <0x43000000 0x0c 0x00000000 0x0c 0x00000000 0x04 0x00000000>;
			#address-cells = <3>;
			#size-cells = <2>;
			bus-range = <0x30 0x5f>;
			device_type = "pci";

			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH 0>,
					<0 0 0 2 &gic 0 0 GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH 0>,
					<0 0 0 3 &gic 0 0 GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH 0>,
					<0 0 0 4 &gic 0 0 GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH 0>;
			msi-map = <0x3000 &gic_its 0x3000 0x3000>;
			status = "disabled";
		};

		gic: interrupt-controller@e010000 {
			compatible = "arm,gic-v3";
			reg = <0x0 0x0e010000 0 0x10000>,	/* GICD */
			      <0x0 0x0e090000 0 0x300000>;       /* GICR * 12 */
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW 0>;
			#interrupt-cells = <4>;
			interrupt-controller;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;

			gic_its: msi-controller@e050000 {
				compatible = "arm,gic-v3-its";
				reg = <0x0 0x0e050000 0x0 0x30000>;
				msi-controller;
				#msi-cells = <1>;
			};

			ppi-partitions {
				ppi_partition0: interrupt-partition-0 {
					affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
				};

				ppi_partition1: interrupt-partition-1 {
					affinity = <&cpu4 &cpu5 &cpu6 &cpu7 &cpu8 &cpu9 &cpu10 &cpu11>;
				};
			};
		};

		iomuxc_s5: pinctrl@16007000 {
			compatible = "cix,sky1-pinctrl-s5";
			reg = <0x0 0x16007000 0x0 0x1000>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>,
			     <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW 0>;
	};
};