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1422 1423 1424 1425 1426 1427 1428 1429 | // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* * IPQ5424 device tree source * * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,apss-ipq.h> #include <dt-bindings/clock/qcom,ipq5424-cmn-pll.h> #include <dt-bindings/clock/qcom,ipq5424-gcc.h> #include <dt-bindings/reset/qcom,ipq5424-gcc.h> #include <dt-bindings/interconnect/qcom,ipq5424.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/thermal/thermal.h> / { #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&intc>; clocks { ref_48mhz_clk: ref-48mhz-clk { compatible = "fixed-factor-clock"; clocks = <&xo_clk>; #clock-cells = <0>; }; sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; }; xo_board: xo-board-clk { compatible = "fixed-factor-clock"; clocks = <&ref_48mhz_clk>; #clock-cells = <0>; }; xo_clk: xo-clk { compatible = "fixed-clock"; #clock-cells = <0>; }; }; cpus: cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0>; enable-method = "psci"; next-level-cache = <&l2_0>; clocks = <&apss_clk APSS_SILVER_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; #cooling-cells = <2>; l2_0: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&l3_0>; l3_0: l3-cache { compatible = "cache"; cache-level = <3>; cache-unified; }; }; }; cpu1: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a55"; enable-method = "psci"; reg = <0x100>; next-level-cache = <&l2_100>; clocks = <&apss_clk APSS_SILVER_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; #cooling-cells = <2>; l2_100: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&l3_0>; }; }; cpu2: cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a55"; enable-method = "psci"; reg = <0x200>; next-level-cache = <&l2_200>; clocks = <&apss_clk APSS_SILVER_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; #cooling-cells = <2>; l2_200: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&l3_0>; }; }; cpu3: cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a55"; enable-method = "psci"; reg = <0x300>; next-level-cache = <&l2_300>; clocks = <&apss_clk APSS_SILVER_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; #cooling-cells = <2>; l2_300: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&l3_0>; }; }; }; firmware { scm { compatible = "qcom,scm-ipq5424", "qcom,scm"; qcom,dload-mode = <&tcsr 0x25100>; }; }; cpu_opp_table: opp-table-cpu { compatible = "operating-points-v2-kryo-cpu"; opp-shared; nvmem-cells = <&cpu_speed_bin>; opp-816000000 { opp-hz = /bits/ 64 <816000000>; opp-microvolt = <850000>; opp-supported-hw = <0x3>; clock-latency-ns = <200000>; opp-peak-kBps = <816000>; }; opp-1416000000 { opp-hz = /bits/ 64 <1416000000>; opp-microvolt = <850000>; opp-supported-hw = <0x3>; clock-latency-ns = <200000>; opp-peak-kBps = <984000>; }; opp-1800000000 { opp-hz = /bits/ 64 <1800000000>; opp-microvolt = <1000000>; opp-supported-hw = <0x1>; clock-latency-ns = <200000>; opp-peak-kBps = <1272000>; }; }; memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ reg = <0x0 0x80000000 0x0 0x0>; }; pmu-a55 { compatible = "arm,cortex-a55-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; }; pmu-dsu { compatible = "arm,dsu-pmu"; interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; bootloader@8a200000 { reg = <0x0 0x8a200000 0x0 0x400000>; no-map; }; tz@8a600000 { reg = <0x0 0x8a600000 0x0 0x200000>; no-map; }; smem@8a800000 { compatible = "qcom,smem"; reg = <0x0 0x8a800000 0x0 0x32000>; no-map; hwlocks = <&tcsr_mutex 3>; }; tfa@8a832000 { reg = <0x0 0x8a832000 0x0 0x80000>; no-map; status = "disabled"; }; }; soc@0 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges = <0 0 0 0 0x10 0>; pcie0_phy: phy@84000 { compatible = "qcom,ipq5424-qmp-gen3x1-pcie-phy", "qcom,ipq9574-qmp-gen3x1-pcie-phy"; reg = <0x0 0x00084000 0x0 0x1000>; clocks = <&gcc GCC_PCIE0_AUX_CLK>, <&gcc GCC_PCIE0_AHB_CLK>, <&gcc GCC_PCIE0_PIPE_CLK>; clock-names = "aux", "cfg_ahb", "pipe"; assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>; assigned-clock-rates = <20000000>; resets = <&gcc GCC_PCIE0_PHY_BCR>, <&gcc GCC_PCIE0PHY_PHY_BCR>; reset-names = "phy", "common"; #clock-cells = <0>; clock-output-names = "gcc_pcie0_pipe_clk_src"; #phy-cells = <0>; status = "disabled"; }; pcie1_phy: phy@8c000 { compatible = "qcom,ipq5424-qmp-gen3x1-pcie-phy", "qcom,ipq9574-qmp-gen3x1-pcie-phy"; reg = <0x0 0x0008c000 0x0 0x1000>; clocks = <&gcc GCC_PCIE1_AUX_CLK>, <&gcc GCC_PCIE1_AHB_CLK>, <&gcc GCC_PCIE1_PIPE_CLK>; clock-names = "aux", "cfg_ahb", "pipe"; assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>; assigned-clock-rates = <20000000>; resets = <&gcc GCC_PCIE1_PHY_BCR>, <&gcc GCC_PCIE1PHY_PHY_BCR>; reset-names = "phy", "common"; #clock-cells = <0>; clock-output-names = "gcc_pcie1_pipe_clk_src"; #phy-cells = <0>; status = "disabled"; }; cmn_pll: clock-controller@9b000 { compatible = "qcom,ipq5424-cmn-pll"; reg = <0 0x0009b000 0 0x800>; clocks = <&ref_48mhz_clk>, <&gcc GCC_CMN_12GPLL_AHB_CLK>, <&gcc GCC_CMN_12GPLL_SYS_CLK>; clock-names = "ref", "ahb", "sys"; #clock-cells = <1>; assigned-clocks = <&cmn_pll IPQ5424_CMN_PLL_CLK>; assigned-clock-rates-u64 = /bits/ 64 <12000000000>; }; efuse@a4000 { compatible = "qcom,ipq5424-qfprom", "qcom,qfprom"; reg = <0 0x000a4000 0 0x741>; #address-cells = <1>; #size-cells = <1>; tsens_sens9_off: s9@3dc { reg = <0x3dc 0x1>; bits = <4 4>; }; tsens_sens10_off: s10@3dd { reg = <0x3dd 0x1>; bits = <0 4>; }; tsens_sens11_off: s11@3dd { reg = <0x3dd 0x1>; bits = <4 4>; }; tsens_sens12_off: s12@3de { reg = <0x3de 0x1>; bits = <0 4>; }; tsens_sens13_off: s13@3de { reg = <0x3de 0x1>; bits = <4 4>; }; tsens_sens14_off: s14@3e5 { reg = <0x3e5 0x2>; bits = <7 4>; }; tsens_sens15_off: s15@3e6 { reg = <0x3e6 0x1>; bits = <3 4>; }; tsens_mode: mode@419 { reg = <0x419 0x1>; bits = <0 3>; }; tsens_base0: base0@419 { reg = <0x419 0x2>; bits = <3 10>; }; tsens_base1: base1@41a { reg = <0x41a 0x2>; bits = <5 10>; }; }; pcie2_phy: phy@f4000 { compatible = "qcom,ipq5424-qmp-gen3x2-pcie-phy", "qcom,ipq9574-qmp-gen3x2-pcie-phy"; reg = <0x0 0x000f4000 0x0 0x2000>; clocks = <&gcc GCC_PCIE2_AUX_CLK>, <&gcc GCC_PCIE2_AHB_CLK>, <&gcc GCC_PCIE2_PIPE_CLK>; clock-names = "aux", "cfg_ahb", "pipe"; assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>; assigned-clock-rates = <20000000>; resets = <&gcc GCC_PCIE2_PHY_BCR>, <&gcc GCC_PCIE2PHY_PHY_BCR>; reset-names = "phy", "common"; #clock-cells = <0>; clock-output-names = "gcc_pcie2_pipe_clk_src"; #phy-cells = <0>; status = "disabled"; }; pcie3_phy: phy@fc000 { compatible = "qcom,ipq5424-qmp-gen3x2-pcie-phy", "qcom,ipq9574-qmp-gen3x2-pcie-phy"; reg = <0x0 0x000fc000 0x0 0x2000>; clocks = <&gcc GCC_PCIE3_AUX_CLK>, <&gcc GCC_PCIE3_AHB_CLK>, <&gcc GCC_PCIE3_PIPE_CLK>; clock-names = "aux", "cfg_ahb", "pipe"; assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>; assigned-clock-rates = <20000000>; resets = <&gcc GCC_PCIE3_PHY_BCR>, <&gcc GCC_PCIE3PHY_PHY_BCR>; reset-names = "phy", "common"; #clock-cells = <0>; clock-output-names = "gcc_pcie3_pipe_clk_src"; #phy-cells = <0>; status = "disabled"; }; tsens: thermal-sensor@4a9000 { compatible = "qcom,ipq5424-tsens"; reg = <0 0x004a9000 0 0x1000>, <0 0x004a8000 0 0x1000>; interrupts = <GIC_SPI 105 IRQ_TYPE_EDGE_RISING>; interrupt-names = "combined"; nvmem-cells = <&tsens_mode>, <&tsens_base0>, <&tsens_base1>, <&tsens_sens9_off>, <&tsens_sens10_off>, <&tsens_sens11_off>, <&tsens_sens12_off>, <&tsens_sens13_off>, <&tsens_sens14_off>, <&tsens_sens15_off>; nvmem-cell-names = "mode", "base0", "base1", "tsens_sens9_off", "tsens_sens10_off", "tsens_sens11_off", "tsens_sens12_off", "tsens_sens13_off", "tsens_sens14_off", "tsens_sens15_off"; #qcom,sensors = <7>; #thermal-sensor-cells = <1>; }; rng: rng@4c3000 { compatible = "qcom,ipq5424-trng", "qcom,trng"; reg = <0 0x004c3000 0 0x1000>; clocks = <&gcc GCC_PRNG_AHB_CLK>; clock-names = "core"; }; system-cache-controller@800000 { compatible = "qcom,ipq5424-llcc"; reg = <0 0x00800000 0 0x200000>; reg-names = "llcc0_base"; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; }; qfprom@a6000 { compatible = "qcom,ipq5424-qfprom", "qcom,qfprom"; reg = <0x0 0x000a6000 0x0 0x1000>; #address-cells = <1>; #size-cells = <1>; cpu_speed_bin: cpu-speed-bin@234 { reg = <0x234 0x1>; bits = <0 8>; }; }; tlmm: pinctrl@1000000 { compatible = "qcom,ipq5424-tlmm"; reg = <0 0x01000000 0 0x300000>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&tlmm 0 0 50>; interrupt-controller; #interrupt-cells = <2>; uart1_pins: uart1-state { pins = "gpio43", "gpio44"; function = "uart1"; drive-strength = <8>; bias-pull-up; }; }; gcc: clock-controller@1800000 { compatible = "qcom,ipq5424-gcc"; reg = <0 0x01800000 0 0x40000>; clocks = <&xo_board>, <&sleep_clk>, <&pcie0_phy>, <&pcie1_phy>, <&pcie2_phy>, <&pcie3_phy>, <0>; #clock-cells = <1>; #reset-cells = <1>; #interconnect-cells = <1>; }; tcsr_mutex: hwlock@1905000 { compatible = "qcom,tcsr-mutex"; reg = <0 0x01905000 0 0x20000>; #hwlock-cells = <1>; }; tcsr: syscon@1937000 { compatible = "qcom,tcsr-ipq5424", "syscon"; reg = <0 0x01937000 0 0x2a000>; }; qupv3: geniqup@1ac0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x01ac0000 0 0x2000>; ranges; clocks = <&gcc GCC_QUPV3_AHB_MST_CLK>, <&gcc GCC_QUPV3_AHB_SLV_CLK>; clock-names = "m-ahb", "s-ahb"; #address-cells = <2>; #size-cells = <2>; uart0: serial@1a80000 { compatible = "qcom,geni-uart"; reg = <0 0x01a80000 0 0x4000>; clocks = <&gcc GCC_QUPV3_UART0_CLK>; clock-names = "se"; interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; uart1: serial@1a84000 { compatible = "qcom,geni-debug-uart"; reg = <0 0x01a84000 0 0x4000>; clocks = <&gcc GCC_QUPV3_UART1_CLK>; clock-names = "se"; interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; }; spi0: spi@1a90000 { compatible = "qcom,geni-spi"; reg = <0 0x01a90000 0 0x4000>; clocks = <&gcc GCC_QUPV3_SPI0_CLK>; clock-names = "se"; interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi1: spi@1a94000 { compatible = "qcom,geni-spi"; reg = <0 0x01a94000 0 0x4000>; clocks = <&gcc GCC_QUPV3_SPI1_CLK>; clock-names = "se"; interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; sdhc: mmc@7804000 { compatible = "qcom,ipq5424-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x07804000 0 0x1000>, <0 0x07805000 0 0x1000>; reg-names = "hc", "cqhci"; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; clock-names = "iface", "core", "xo"; supports-cqe; status = "disabled"; }; intc: interrupt-controller@f200000 { compatible = "arm,gic-v3"; reg = <0 0xf200000 0 0x10000>, /* GICD */ <0 0xf240000 0 0x80000>; /* GICR * 4 regions */ #address-cells = <0>; #interrupt-cells = <0x3>; interrupt-controller; #redistributor-regions = <1>; redistributor-stride = <0x0 0x20000>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; mbi-ranges = <672 128>; msi-controller; }; watchdog@f410000 { compatible = "qcom,apss-wdt-ipq5424", "qcom,kpss-wdt"; reg = <0 0x0f410000 0 0x1000>; interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; clocks = <&sleep_clk>; }; qusb_phy_1: phy@71000 { compatible = "qcom,ipq5424-qusb2-phy"; reg = <0 0x00071000 0 0x180>; #phy-cells = <0>; clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, <&xo_board>; clock-names = "cfg_ahb", "ref"; resets = <&gcc GCC_QUSB2_1_PHY_BCR>; status = "disabled"; }; usb2: usb2@1e00000 { compatible = "qcom,ipq5424-dwc3", "qcom,dwc3"; reg = <0 0x01ef8800 0 0x400>; #address-cells = <2>; #size-cells = <2>; ranges; clocks = <&gcc GCC_USB1_MASTER_CLK>, <&gcc GCC_USB1_SLEEP_CLK>, <&gcc GCC_USB1_MOCK_UTMI_CLK>, <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, <&gcc GCC_CNOC_USB_CLK>; clock-names = "core", "sleep", "mock_utmi", "iface", "cfg_noc"; assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>, <&gcc GCC_USB1_MOCK_UTMI_CLK>; assigned-clock-rates = <200000000>, <24000000>; interrupts-extended = <&intc GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pwr_event", "qusb2_phy", "dm_hs_phy_irq", "dp_hs_phy_irq"; resets = <&gcc GCC_USB1_BCR>; qcom,select-utmi-as-pipe-clk; status = "disabled"; dwc_1: usb@1e00000 { compatible = "snps,dwc3"; reg = <0 0x01e00000 0 0xe000>; clocks = <&gcc GCC_USB1_MOCK_UTMI_CLK>; clock-names = "ref"; interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; phys = <&qusb_phy_1>; phy-names = "usb2-phy"; tx-fifo-resize; snps,is-utmi-l1-suspend; snps,hird-threshold = /bits/ 8 <0x0>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; }; }; qusb_phy_0: phy@7b000 { compatible = "qcom,ipq5424-qusb2-phy"; reg = <0 0x0007b000 0 0x180>; #phy-cells = <0>; clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo_board>; clock-names = "cfg_ahb", "ref"; resets = <&gcc GCC_QUSB2_0_PHY_BCR>; status = "disabled"; }; ssphy_0: phy@7d000 { compatible = "qcom,ipq5424-qmp-usb3-phy"; reg = <0 0x0007d000 0 0xa00>; #phy-cells = <0>; clocks = <&gcc GCC_USB0_AUX_CLK>, <&xo_board>, <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&gcc GCC_USB0_PIPE_CLK>; clock-names = "aux", "ref", "cfg_ahb", "pipe"; resets = <&gcc GCC_USB0_PHY_BCR>, <&gcc GCC_USB3PHY_0_PHY_BCR>; reset-names = "phy", "phy_phy"; #clock-cells = <0>; clock-output-names = "usb0_pipe_clk"; status = "disabled"; }; usb3: usb3@8a00000 { compatible = "qcom,ipq5424-dwc3", "qcom,dwc3"; reg = <0 0x08af8800 0 0x400>; #address-cells = <2>; #size-cells = <2>; ranges; clocks = <&gcc GCC_USB0_MASTER_CLK>, <&gcc GCC_USB0_SLEEP_CLK>, <&gcc GCC_USB0_MOCK_UTMI_CLK>, <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&gcc GCC_CNOC_USB_CLK>; clock-names = "core", "sleep", "mock_utmi", "iface", "cfg_noc"; assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>, <&gcc GCC_USB0_MOCK_UTMI_CLK>; assigned-clock-rates = <200000000>, <24000000>; interrupts-extended = <&intc GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pwr_event", "qusb2_phy", "dm_hs_phy_irq", "dp_hs_phy_irq"; resets = <&gcc GCC_USB_BCR>; status = "disabled"; dwc_0: usb@8a00000 { compatible = "snps,dwc3"; reg = <0 0x08a00000 0 0xcd00>; clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; clock-names = "ref"; interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; phys = <&qusb_phy_0>, <&ssphy_0>; phy-names = "usb2-phy", "usb3-phy"; tx-fifo-resize; snps,is-utmi-l1-suspend; snps,hird-threshold = /bits/ 8 <0x0>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; }; }; timer@f420000 { compatible = "arm,armv7-timer-mem"; reg = <0 0xf420000 0 0x1000>; ranges = <0 0 0 0x10000000>; #address-cells = <1>; #size-cells = <1>; frame@f421000 { reg = <0xf421000 0x1000>, <0xf422000 0x1000>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; frame-number = <0>; }; frame@f423000 { reg = <0xf423000 0x1000>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; frame-number = <1>; status = "disabled"; }; frame@f425000 { reg = <0xf425000 0x1000>, <0xf426000 0x1000>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; frame-number = <2>; status = "disabled"; }; frame@f427000 { reg = <0xf427000 0x1000>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; frame-number = <3>; status = "disabled"; }; frame@f429000 { reg = <0xf429000 0x1000>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; frame-number = <4>; status = "disabled"; }; frame@f42b000 { reg = <0xf42b000 0x1000>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; frame-number = <5>; status = "disabled"; }; frame@f42d000 { reg = <0xf42d000 0x1000>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; frame-number = <6>; status = "disabled"; }; }; apss_clk: clock-controller@fa80000 { compatible = "qcom,ipq5424-apss-clk"; reg = <0x0 0x0fa80000 0x0 0x20000>; clocks = <&xo_board>, <&gcc GPLL0>; #clock-cells = <1>; #interconnect-cells = <1>; }; clock-controller@39b00000 { compatible = "qcom,ipq5424-nsscc"; reg = <0 0x39b00000 0 0x100000>; clocks = <&cmn_pll IPQ5424_XO_24MHZ_CLK>, <&cmn_pll IPQ5424_NSS_300MHZ_CLK>, <&cmn_pll IPQ5424_PPE_375MHZ_CLK>, <&gcc GPLL0_OUT_AUX>, <0>, <0>, <0>, <0>, <0>, <0>, <&gcc GCC_NSSCC_CLK>; clock-names = "xo", "nss", "ppe", "gpll0_out", "uniphy0_rx", "uniphy0_tx", "uniphy1_rx", "uniphy1_tx", "uniphy2_rx", "uniphy2_tx", "bus"; #clock-cells = <1>; #reset-cells = <1>; #interconnect-cells = <1>; }; pcie3: pcie@40000000 { compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574"; reg = <0x0 0x40000000 0x0 0xf1c>, <0x0 0x40000f20 0x0 0xa8>, <0x0 0x40001000 0x0 0x1000>, <0x0 0x000f8000 0x0 0x3000>, <0x0 0x40100000 0x0 0x1000>, <0x0 0x000fe000 0x0 0x1000>; reg-names = "dbi", "elbi", "atu", "parf", "config", "mhi"; device_type = "pci"; linux,pci-domain = <3>; num-lanes = <2>; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x00100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x0fd00000>; msi-map = <0x0 &intc 0x0 0x1000>; interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi0", "msi1", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7", "global"; #interrupt-cells = <1>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0 0 0 1 &intc GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 2 &intc GIC_SPI 480 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 3 &intc GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &intc GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE3_AXI_M_CLK>, <&gcc GCC_PCIE3_AXI_S_CLK>, <&gcc GCC_PCIE3_AXI_S_BRIDGE_CLK>, <&gcc GCC_PCIE3_RCHNG_CLK>, <&gcc GCC_PCIE3_AHB_CLK>, <&gcc GCC_PCIE3_AUX_CLK>; clock-names = "axi_m", "axi_s", "axi_bridge", "rchng", "ahb", "aux"; assigned-clocks = <&gcc GCC_PCIE3_RCHNG_CLK>; assigned-clock-rates = <100000000>; resets = <&gcc GCC_PCIE3_PIPE_ARES>, <&gcc GCC_PCIE3_CORE_STICKY_RESET>, <&gcc GCC_PCIE3_AXI_S_STICKY_RESET>, <&gcc GCC_PCIE3_AXI_S_ARES>, <&gcc GCC_PCIE3_AXI_M_STICKY_RESET>, <&gcc GCC_PCIE3_AXI_M_ARES>, <&gcc GCC_PCIE3_AUX_ARES>, <&gcc GCC_PCIE3_AHB_ARES>; reset-names = "pipe", "sticky", "axi_s_sticky", "axi_s", "axi_m_sticky", "axi_m", "aux", "ahb"; phys = <&pcie3_phy>; phy-names = "pciephy"; interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>, <&gcc MASTER_CNOC_PCIE3 &gcc SLAVE_CNOC_PCIE3>; interconnect-names = "pcie-mem", "cpu-pcie"; status = "disabled"; pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; #address-cells = <3>; #size-cells = <2>; ranges; }; }; pcie2: pcie@50000000 { compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574"; reg = <0x0 0x50000000 0x0 0xf1c>, <0x0 0x50000f20 0x0 0xa8>, <0x0 0x50001000 0x0 0x1000>, <0x0 0x000f0000 0x0 0x3000>, <0x0 0x50100000 0x0 0x1000>, <0x0 0x000f6000 0x0 0x1000>; reg-names = "dbi", "elbi", "atu", "parf", "config", "mhi"; device_type = "pci"; linux,pci-domain = <2>; num-lanes = <2>; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x50200000 0x0 0x00100000>, <0x02000000 0x0 0x50300000 0x0 0x50300000 0x0 0x0fd00000>; msi-map = <0x0 &intc 0x0 0x1000>; interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi0", "msi1", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7", "global"; #interrupt-cells = <1>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0 0 0 1 &intc GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 2 &intc GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 3 &intc GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &intc GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE2_AXI_M_CLK>, <&gcc GCC_PCIE2_AXI_S_CLK>, <&gcc GCC_PCIE2_AXI_S_BRIDGE_CLK>, <&gcc GCC_PCIE2_RCHNG_CLK>, <&gcc GCC_PCIE2_AHB_CLK>, <&gcc GCC_PCIE2_AUX_CLK>; clock-names = "axi_m", "axi_s", "axi_bridge", "rchng", "ahb", "aux"; assigned-clocks = <&gcc GCC_PCIE2_RCHNG_CLK>; assigned-clock-rates = <100000000>; resets = <&gcc GCC_PCIE2_PIPE_ARES>, <&gcc GCC_PCIE2_CORE_STICKY_RESET>, <&gcc GCC_PCIE2_AXI_S_STICKY_RESET>, <&gcc GCC_PCIE2_AXI_S_ARES>, <&gcc GCC_PCIE2_AXI_M_STICKY_RESET>, <&gcc GCC_PCIE2_AXI_M_ARES>, <&gcc GCC_PCIE2_AUX_ARES>, <&gcc GCC_PCIE2_AHB_ARES>; reset-names = "pipe", "sticky", "axi_s_sticky", "axi_s", "axi_m_sticky", "axi_m", "aux", "ahb"; phys = <&pcie2_phy>; phy-names = "pciephy"; interconnects = <&gcc MASTER_ANOC_PCIE2 &gcc SLAVE_ANOC_PCIE2>, <&gcc MASTER_CNOC_PCIE2 &gcc SLAVE_CNOC_PCIE2>; interconnect-names = "pcie-mem", "cpu-pcie"; status = "disabled"; pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; #address-cells = <3>; #size-cells = <2>; ranges; }; }; pcie1: pcie@60000000 { compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574"; reg = <0x0 0x60000000 0x0 0xf1c>, <0x0 0x60000f20 0x0 0xa8>, <0x0 0x60001000 0x0 0x1000>, <0x0 0x00088000 0x0 0x3000>, <0x0 0x60100000 0x0 0x1000>, <0x0 0x0008e000 0x0 0x1000>; reg-names = "dbi", "elbi", "atu", "parf", "config", "mhi"; device_type = "pci"; linux,pci-domain = <1>; num-lanes = <1>; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x00100000>, <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x0fd00000>; msi-map = <0x0 &intc 0x0 0x1000>; interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi0", "msi1", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7", "global"; #interrupt-cells = <1>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0 0 0 1 &intc GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 2 &intc GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 3 &intc GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &intc GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE1_AXI_M_CLK>, <&gcc GCC_PCIE1_AXI_S_CLK>, <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>, <&gcc GCC_PCIE1_RCHNG_CLK>, <&gcc GCC_PCIE1_AHB_CLK>, <&gcc GCC_PCIE1_AUX_CLK>; clock-names = "axi_m", "axi_s", "axi_bridge", "rchng", "ahb", "aux"; assigned-clocks = <&gcc GCC_PCIE1_RCHNG_CLK>; assigned-clock-rates = <100000000>; resets = <&gcc GCC_PCIE1_PIPE_ARES>, <&gcc GCC_PCIE1_CORE_STICKY_RESET>, <&gcc GCC_PCIE1_AXI_S_STICKY_RESET>, <&gcc GCC_PCIE1_AXI_S_ARES>, <&gcc GCC_PCIE1_AXI_M_STICKY_RESET>, <&gcc GCC_PCIE1_AXI_M_ARES>, <&gcc GCC_PCIE1_AUX_ARES>, <&gcc GCC_PCIE1_AHB_ARES>; reset-names = "pipe", "sticky", "axi_s_sticky", "axi_s", "axi_m_sticky", "axi_m", "aux", "ahb"; phys = <&pcie1_phy>; phy-names = "pciephy"; interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>, <&gcc MASTER_CNOC_PCIE1 &gcc SLAVE_CNOC_PCIE1>; interconnect-names = "pcie-mem", "cpu-pcie"; status = "disabled"; pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; #address-cells = <3>; #size-cells = <2>; ranges; }; }; pcie0: pcie@70000000 { compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574"; reg = <0x0 0x70000000 0x0 0xf1c>, <0x0 0x70000f20 0x0 0xa8>, <0x0 0x70001000 0x0 0x1000>, <0x0 0x00080000 0x0 0x3000>, <0x0 0x70100000 0x0 0x1000>, <0x0 0x00086000 0x0 0x1000>; reg-names = "dbi", "elbi", "atu", "parf", "config", "mhi"; device_type = "pci"; linux,pci-domain = <0>; num-lanes = <1>; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x00100000>, <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x0fd00000>; msi-map = <0x0 &intc 0x0 0x1000>; interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi0", "msi1", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7", "global"; #interrupt-cells = <1>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 3 &intc GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &intc GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE0_AXI_M_CLK>, <&gcc GCC_PCIE0_AXI_S_CLK>, <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, <&gcc GCC_PCIE0_RCHNG_CLK>, <&gcc GCC_PCIE0_AHB_CLK>, <&gcc GCC_PCIE0_AUX_CLK>; clock-names = "axi_m", "axi_s", "axi_bridge", "rchng", "ahb", "aux"; assigned-clocks = <&gcc GCC_PCIE0_RCHNG_CLK>; assigned-clock-rates = <100000000>; resets = <&gcc GCC_PCIE0_PIPE_ARES>, <&gcc GCC_PCIE0_CORE_STICKY_RESET>, <&gcc GCC_PCIE0_AXI_S_STICKY_RESET>, <&gcc GCC_PCIE0_AXI_S_ARES>, <&gcc GCC_PCIE0_AXI_M_STICKY_RESET>, <&gcc GCC_PCIE0_AXI_M_ARES>, <&gcc GCC_PCIE0_AUX_ARES>, <&gcc GCC_PCIE0_AHB_ARES>; reset-names = "pipe", "sticky", "axi_s_sticky", "axi_s", "axi_m_sticky", "axi_m", "aux", "ahb"; phys = <&pcie0_phy>; phy-names = "pciephy"; interconnects = <&gcc MASTER_ANOC_PCIE0 &gcc SLAVE_ANOC_PCIE0>, <&gcc MASTER_CNOC_PCIE0 &gcc SLAVE_CNOC_PCIE0>; interconnect-names = "pcie-mem", "cpu-pcie"; status = "disabled"; pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; #address-cells = <3>; #size-cells = <2>; ranges; }; }; }; thermal_zones: thermal-zones { cpu0-thermal { polling-delay-passive = <100>; thermal-sensors = <&tsens 14>; trips { cpu0_crit: cpu-critical { temperature = <120000>; hysteresis = <9000>; type = "critical"; }; cpu0_alert: cpu-passive { temperature = <110000>; hysteresis = <9000>; type = "passive"; }; }; cooling-maps { map0 { trip = <&cpu0_alert>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu1-thermal { polling-delay-passive = <100>; thermal-sensors = <&tsens 12>; trips { cpu1_crit: cpu-critical { temperature = <120000>; hysteresis = <9000>; type = "critical"; }; cpu1_alert: cpu-passive { temperature = <110000>; hysteresis = <9000>; type = "passive"; }; }; cooling-maps { map0 { trip = <&cpu1_alert>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu2-thermal { polling-delay-passive = <100>; thermal-sensors = <&tsens 11>; trips { cpu2_crit: cpu-critical { temperature = <120000>; hysteresis = <9000>; type = "critical"; }; cpu2_alert: cpu-passive { temperature = <110000>; hysteresis = <9000>; type = "passive"; }; }; cooling-maps { map0 { trip = <&cpu2_alert>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu3-thermal { polling-delay-passive = <100>; thermal-sensors = <&tsens 13>; trips { cpu3_crit: cpu-critical { temperature = <120000>; hysteresis = <9000>; type = "critical"; }; cpu3_alert: cpu-passive { temperature = <110000>; hysteresis = <9000>; type = "passive"; }; }; cooling-maps { map0 { trip = <&cpu3_alert>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; wcss-tile2-thermal { thermal-sensors = <&tsens 9>; trips { wcss-tile2-critical { temperature = <125000>; hysteresis = <9000>; type = "critical"; }; }; }; wcss-tile3-thermal { thermal-sensors = <&tsens 10>; trips { wcss-tile3-critical { temperature = <125000>; hysteresis = <9000>; type = "critical"; }; }; }; top-glue-thermal { thermal-sensors = <&tsens 15>; trips { top-glue-critical { temperature = <125000>; hysteresis = <9000>; type = "critical"; }; }; }; }; timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; }; }; |