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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 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run-time. */ /* RCE1 */ li t0, MEM_STCFG1 li t1, 0x00000083 sw t1, 0(t0) li t0, MEM_STTIME1 li t1, 0x33030A10 sw t1, 0(t0) li t0, MEM_STADDR1 li t1, 0x11803E40 sw t1, 0(t0) /* Set DSTRB bits so switch will read correctly */ li t1, 0xBE00000C lw t2, 0(t1) or t2, t2, 0x00000300 sw t2, 0(t1) /* Check switch setting */ li t1, 0xBE000014 lw t2, 0(t1) and t2, t2, 0x00000100 bne t2, zero, big_endian nop little_endian: /* Change Au1 core to little endian */ li t0, AU1500_SYS_ADDR li t1, 1 sw t1, sys_endian(t0) mfc0 t2, CP0_CONFIG mtc0 t2, CP0_CONFIG nop nop /* Big Endian is default so nothing to do but fall through */ big_endian: /* * Step 2) Establish Status Register * (set BEV, clear ERL, clear EXL, clear IE) */ li t1, 0x00400000 mtc0 t1, CP0_STATUS /* * Step 3) Establish CP0 Config0 * (set OD, set K0=3) */ li t1, 0x00080003 mtc0 t1, CP0_CONFIG /* * Step 4) Disable Watchpoint facilities */ li t1, 0x00000000 mtc0 t1, CP0_WATCHLO mtc0 t1, CP0_IWATCHLO /* * Step 5) Disable the performance counters */ mtc0 zero, CP0_PERFORMANCE nop /* * Step 6) Establish EJTAG Debug register */ mtc0 zero, CP0_DEBUG nop /* * Step 7) Establish Cause * (set IV bit) */ li t1, 0x00800000 mtc0 t1, CP0_CAUSE /* Establish Wired (and Random) */ mtc0 zero, CP0_WIRED nop /* First setup pll:s to make serial work ok */ /* We have a 12 MHz crystal */ li t0, SYS_CPUPLL li t1, 0x21 /* 396 MHz */ sw t1, 0(t0) sync nop nop /* wait 1mS for clocks to settle */ li t1, MEM_1MS 1: add t1, -1 bne t1, zero, 1b nop /* Setup AUX PLL */ li t0, SYS_AUXPLL li t1, 8 /* 96 MHz */ sw t1, 0(t0) /* aux pll */ sync /* Static memory controller */ /* RCE0 8MB AMD29D323 Flash */ li t0, MEM_STCFG0 li t1, 0x00001403 sw t1, 0(t0) li t0, MEM_STTIME0 li t1, 0xFFFFFFDD sw t1, 0(t0) li t0, MEM_STADDR0 li t1, 0x11F83FE0 sw t1, 0(t0) /* RCE1 CPLD Board Logic */ li t0, MEM_STCFG1 li t1, 0x00000083 sw t1, 0(t0) li t0, MEM_STTIME1 li t1, 0x33030A10 sw t1, 0(t0) li t0, MEM_STADDR1 li t1, 0x11803E40 sw t1, 0(t0) /* RCE2 CPLD Board Logic */ li t0, MEM_STCFG2 li t1, 0x00000004 sw t1, 0(t0) li t0, MEM_STTIME2 li t1, 0x08061908 sw t1, 0(t0) li t0, MEM_STADDR2 li t1, 0x12A03FC0 sw t1, 0(t0) /* RCE3 PCMCIA 250ns */ li t0, MEM_STCFG3 li t1, 0x00000002 sw t1, 0(t0) li t0, MEM_STTIME3 li t1, 0x280E3E07 sw t1, 0(t0) li t0, MEM_STADDR3 li t1, 0x10000000 sw t1, 0(t0) sync /* Set peripherals to a known state */ li t0, IC0_CFG0CLR li t1, 0xFFFFFFFF sw t1, 0(t0) li t0, IC0_CFG0CLR sw t1, 0(t0) li t0, IC0_CFG1CLR sw t1, 0(t0) li t0, IC0_CFG2CLR sw t1, 0(t0) li t0, IC0_SRCSET sw t1, 0(t0) li t0, IC0_ASSIGNSET sw t1, 0(t0) li t0, IC0_WAKECLR sw t1, 0(t0) li t0, IC0_RISINGCLR sw t1, 0(t0) li t0, IC0_FALLINGCLR sw t1, 0(t0) li t0, IC0_TESTBIT li t1, 0x00000000 sw t1, 0(t0) sync li t0, IC1_CFG0CLR li t1, 0xFFFFFFFF sw t1, 0(t0) li t0, IC1_CFG0CLR sw t1, 0(t0) li t0, IC1_CFG1CLR sw t1, 0(t0) li t0, IC1_CFG2CLR sw t1, 0(t0) li t0, IC1_SRCSET sw t1, 0(t0) li t0, IC1_ASSIGNSET sw t1, 0(t0) li t0, IC1_WAKECLR sw t1, 0(t0) li t0, IC1_RISINGCLR sw t1, 0(t0) li t0, IC1_FALLINGCLR sw t1, 0(t0) li t0, IC1_TESTBIT li t1, 0x00000000 sw t1, 0(t0) sync li t0, SYS_FREQCTRL0 li t1, 0x00000000 sw t1, 0(t0) li t0, SYS_FREQCTRL1 li t1, 0x00000000 sw t1, 0(t0) li t0, SYS_CLKSRC li t1, 0x00000000 sw t1, 0(t0) li t0, SYS_PININPUTEN li t1, 0x00000000 sw t1, 0(t0) sync li t0, 0xB1100100 li t1, 0x00000000 sw t1, 0(t0) li t0, 0xB1400100 li t1, 0x00000000 sw t1, 0(t0) li t0, SYS_WAKEMSK li t1, 0x00000000 sw t1, 0(t0) li t0, SYS_WAKESRC li t1, 0x00000000 sw t1, 0(t0) /* wait 1mS before setup */ li t1, MEM_1MS 1: add t1, -1 bne t1, zero, 1b nop /* * Skip memory setup if we are running from memory */ li t0, 0x90000000 sub t0, ra, t0 bltz t0, skip_memsetup nop /* * SDCS0 - Not used, for SMROM * SDCS1 - 32MB Micron 48LCBM16A2 * SDCS2 - 32MB Micron 48LCBM16A2 */ li t0, MEM_SDMODE0 li t1, 0x00000000 sw t1, 0(t0) li t0, MEM_SDMODE1 li t1, 0x00552229 sw t1, 0(t0) li t0, MEM_SDMODE2 li t1, 0x00552229 sw t1, 0(t0) li t0, MEM_SDADDR0 li t1, 0x00000000 sw t1, 0(t0) li t0, MEM_SDADDR1 li t1, 0x001003F8 sw t1, 0(t0) li t0, MEM_SDADDR2 li t1, 0x001023F8 sw t1, 0(t0) sync li t0, MEM_SDREFCFG li t1, 0x74000c30 /* Disable */ sw t1, 0(t0) sync li t0, MEM_SDPRECMD sw zero, 0(t0) sync li t0, MEM_SDAUTOREF sw zero, 0(t0) sync sw zero, 0(t0) sync li t0, MEM_SDREFCFG li t1, 0x76000c30 /* Enable */ sw t1, 0(t0) sync li t0, MEM_SDWRMD0 li t1, 0x00000023 sw t1, 0(t0) sync li t0, MEM_SDWRMD1 li t1, 0x00000023 sw t1, 0(t0) sync li t0, MEM_SDWRMD2 li t1, 0x00000023 sw t1, 0(t0) sync /* wait 1mS after setup */ li t1, MEM_1MS 1: add t1, -1 bne t1, zero, 1b nop skip_memsetup: li t0, SYS_PINFUNC li t1, 0/*0x00008080*/ sw t1, 0(t0) /* li t0, SYS_TRIOUTCLR li t1, 0x00001FFF sw t1, 0(t0) li t0, SYS_OUTPUTCLR li t1, 0x00008000 sw t1, 0(t0) */ sync j ra nop |