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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 | /* * (C) Copyright 2006 DENX Software Engineering * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ #include <config.h> #include <version.h> #include <asm/arch/pxa-regs.h> DRAM_SIZE: .long CFG_DRAM_SIZE .macro wait time ldr r2, =OSCR mov r3, #0 str r3, [r2] 0: ldr r3, [r2] cmp r3, \time bls 0b .endm .globl lowlevel_init lowlevel_init: /* Set up GPIO pins first */ mov r10, lr /* Configure GPIO Pins 97, 98 UART1 / altern. Fkt. 1 */ ldr r0, =GPIO97 ldr r1, =0x801 str r1, [r0] ldr r0, =GPIO98 ldr r1, =0x801 str r1, [r0] /* tebrandt - ASCR, clear the RDH bit */ ldr r0, =ASCR ldr r1, [r0] bic r1, r1, #0x80000000 str r1, [r0] mem_init: /* Configure ACCR Register - enable DMEMC Clock at 260 / 2 MHz */ ldr r0, =ACCR ldr r1, [r0] orr r1, r1, #0x3000 str r1, [r0] ldr r1, [r0] /* 2. Programm MDCNFG, leaving DMCEN de-asserted */ ldr r0, =MDCNFG ldr r1, =(MDCNFG_DMAP | MDCNFG_DTYPE | MDCNFG_DTC_2 | MDCNFG_DCSE0 | MDCNFG_DRAC_13) /* ldr r1, =0x80000403 */ str r1, [r0] ldr r1, [r0] /* delay until written */ /* 3. wait nop power up waiting period (200ms) * optimization: Steps 4+6 can be done during this */ wait #300 /* 4. Perform an initial Rcomp-calibration cycle */ ldr r0, =RCOMP ldr r1, =0x80000000 str r1, [r0] ldr r1, [r0] /* delay until written */ /* missing: program for automatic rcomp evaluation cycles */ /* 5. DDR DRAM strobe delay calibration */ ldr r0, =DDR_HCAL ldr r1, =0x88000007 str r1, [r0] wait #5 ldr r1, [r0] /* delay until written */ /* Set MDMRS */ ldr r0, =MDMRS ldr r1, =0x60000033 str r1, [r0] wait #300 /* Configure MDREFR */ ldr r0, =MDREFR ldr r1, =0x00000006 str r1, [r0] ldr r1, [r0] /* Enable the dynamic memory controller */ ldr r0, =MDCNFG ldr r1, [r0] orr r1, r1, #MDCNFG_DMCEN str r1, [r0] #ifndef CFG_SKIP_DRAM_SCRUB /* scrub/init SDRAM if enabled/present */ ldr r8, =CFG_DRAM_BASE /* base address of SDRAM (CFG_DRAM_BASE) */ ldr r9, =CFG_DRAM_SIZE /* size of memory to scrub (CFG_DRAM_SIZE) */ mov r0, #0 /* scrub with 0x0000:0000 */ mov r1, #0 mov r2, #0 mov r3, #0 mov r4, #0 mov r5, #0 mov r6, #0 mov r7, #0 10: /* fastScrubLoop */ subs r9, r9, #32 /* 8 words/line */ stmia r8!, {r0-r7} beq 15f b 10b #endif /* CFG_SKIP_DRAM_SCRUB */ 15: /* Mask all interrupts */ mov r1, #0 mcr p6, 0, r1, c1, c0, 0 @ ICMR /* Disable software and data breakpoints */ mov r0, #0 mcr p15,0,r0,c14,c8,0 /* ibcr0 */ mcr p15,0,r0,c14,c9,0 /* ibcr1 */ mcr p15,0,r0,c14,c4,0 /* dbcon */ /* Enable all debug functionality */ mov r0,#0x80000000 mcr p14,0,r0,c10,c0,0 /* dcsr */ endlowlevel_init: mov pc, lr |