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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 | /*------------------------------------------------------------------------------+ * * This souce code has been made available to you by EuroDesign * (www.eurodsn.de). It's based on the original IBM source code, so * this follows: * * This source code has been made available to you by IBM on an AS-IS * basis. Anyone receiving this source is licensed under IBM * copyrights to use it in any way he or she deems fit, including * copying it, modifying it, compiling it, and redistributing it either * with or without modifications. No license under IBM patents or * patent applications is to be implied by the copyright license. * * Any user of this software should understand that IBM cannot provide * technical support for this software and will not be responsible for * any consequences resulting from the use of this software. * * Any person who transfers this source code or any derivative work * must include the IBM copyright notice, this paragraph, and the * preceding two paragraphs in the transferred software. * * COPYRIGHT I B M CORPORATION 1995 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M *------------------------------------------------------------------------------- */ #include <config.h> #include <ppc4xx.h> #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include <ppc_asm.tmpl> #include <ppc_defs.h> #include <asm/cache.h> #include <asm/mmu.h> /** * ext_bus_cntlr_init - Initializes the External Bus Controller for the external peripherals * * IMPORTANT: For pass1 this code must run from cache since you can not * reliably change a peripheral banks timing register (pbxap) while running * code from that bank. For ex., since we are running from ROM on bank 0, we * can NOT execute the code that modifies bank 0 timings from ROM, so * we run it from cache. * * Bank 0 - Boot-Flash * Bank 1 - NAND-Flash * Bank 2 - ISA bus * Bank 3 - Second Flash * Bank 4 - USB controller */ .globl ext_bus_cntlr_init ext_bus_cntlr_init: /* * We need the current boot up configuration to set correct * timings into internal flash and external flash */ mfdcr r24,strap /* xxxx xxxx xxxx xxx? ?xxx xxxx xxxx xxxx 0 0 -> 8 bit external ROM 0 1 -> 16 bit internal ROM */ addi r4,0,2 srw r24,r24,r4 /* shift right r24 two positions */ andi. r24,r24,0x06000 /* * All calculations are based on 33MHz EBC clock. * * First, create a "very slow" timing (~250ns) with burst mode enabled * This is need for the external flash access */ lis r25,0x0800 ori r25,r25,0x0280 /* 0000 1000 0xxx 0000 0000 0010 100x xxxx = 0x03800280 /* * Second, create a fast timing: * 90ns first cycle - 3 clock access * and 90ns burst cycle, plus 1 clock after the last access * This is used for the internal access */ lis r26,0x8900 ori r26,r26,0x0280 /* 1000 1001 0xxx 0000 0000 0010 100x xxxx /* * We can't change settings on CS# if we currently use them. * -> load a few instructions into cache and run this code from cache */ mflr r4 /* save link register */ bl ..getAddr ..getAddr: mflr r3 /* get address of ..getAddr */ mtlr r4 /* restore link register */ addi r4,0,14 /* set ctr to 10; used to prefetch */ mtctr r4 /* 10 cache lines to fit this function in cache (gives us 8x10=80 instructions) */ ..ebcloop: icbt r0,r3 /* prefetch cache line for addr in r3 */ addi r3,r3,32 /* move to next cache line */ bdnz ..ebcloop /* continue for 10 cache lines */ /* * Delay to ensure all accesses to ROM are complete before changing * bank 0 timings. 200usec should be enough. * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */ lis r3,0x0 ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ mtctr r3 ..spinlp: bdnz ..spinlp /* spin loop */ /*----------------------------------------------------------------------- * Memory Bank 0 (BOOT-ROM) initialization * 0xFFEF00000....0xFFFFFFF * We only have to change the timing. Mapping is ok by boot-strapping *----------------------------------------------------------------------- */ li r4,pb0ap /* PB0AP=Peripheral Bank 0 Access Parameters */ mtdcr ebccfga,r4 mr r4,r26 /* assume internal fast flash is boot flash */ cmpwi r24,0x2000 /* assumption true? ... */ beq 1f /* ...yes! */ mr r4,r25 /* ...no, use the slow variant */ mr r25,r26 /* use this for the other flash */ 1: mtdcr ebccfgd,r4 /* change timing now */ li r4,pb0cr /* PB0CR=Peripheral Bank 0 Control Register */ mtdcr ebccfga,r4 mfdcr r4,ebccfgd lis r3,0x0001 ori r3,r3,0x8000 /* allow reads and writes */ or r4,r4,r3 mtdcr ebccfgd,r4 /*----------------------------------------------------------------------- * Memory Bank 3 (Second-Flash) initialization * 0xF0000000...0xF01FFFFF -> 2MB *----------------------------------------------------------------------- */ li r4,pb3ap /* Peripheral Bank 1 Access Parameter */ mtdcr ebccfga,r4 mtdcr ebccfgd,r2 /* change timing */ li r4,pb3cr /* Peripheral Bank 1 Configuration Registers */ mtdcr ebccfga,r4 lis r4,0xF003 ori r4,r4,0x8000 /* * Consider boot configuration */ xori r24,r24,0x2000 /* invert current bus width */ or r4,r4,r24 mtdcr ebccfgd,r4 /*----------------------------------------------------------------------- * Memory Bank 1 (NAND-Flash) initialization * 0x77D00000...0x77DFFFFF -> 1MB * - the write/read pulse to the NAND can be as short as 25ns, bus the cycle time is always 50ns * - the setup time is 0ns * - the hold time is 15ns * -> * - TWT = 0 * - CSN = 0 * - OEN = 0 * - WBN = 0 * - WBF = 0 * - TH = 1 * ----> 2 clocks per cycle = 60ns cycle (30ns active, 30ns hold) *----------------------------------------------------------------------- */ li r4,pb1ap /* Peripheral Bank 1 Access Parameter */ mtdcr ebccfga,r4 lis r4,0x0000 ori r4,r4,0x0200 mtdcr ebccfgd,r4 li r4,pb1cr /* Peripheral Bank 1 Configuration Registers */ mtdcr ebccfga,r4 lis r4,0x77D1 ori r4,r4,0x8000 mtdcr ebccfgd,r4 /* USB init (without acceleration) */ #ifndef CONFIG_ISP1161_PRESENT li r4,pb4ap /* PB4AP=Peripheral Bank 4 Access Parameters */ mtdcr ebccfga,r4 lis r4,0x0180 ori r4,r4,0x5940 mtdcr ebccfgd,r4 #endif /*----------------------------------------------------------------------- * Memory Bank 2 (ISA Access) initialization (plus memory bank 6 and 7) * 0x78000000...0x7BFFFFFF -> 64 MB * Wir arbeiten bei 33 MHz -> 30ns *----------------------------------------------------------------------- A7 (ppc notation) or A24 (standard notation) decides about the type of access: A7/A24=0 -> memory cycle A7/ /A24=1 -> I/O cycle */ li r4,pb2ap /* PB2AP=Peripheral Bank 2 Access Parameters */ mtdcr ebccfga,r4 /* We emulate an ISA access 1. Address active 2. wait 0 EBC clocks -> CSN=0 3. set CS# 4. wait 0 EBC clock -> OEN/WBN=0 5. set OE#/WE# 6. wait 4 clocks (ca. 90ns) and for Ready signal 7. hold for 4 clocks -> TH=4 */ #if 1 /* faster access to isa-bus */ lis r4,0x0180 ori r4,r4,0x5940 #else lis r4,0x0100 ori r4,r4,0x0340 #endif mtdcr ebccfgd,r4 #ifdef IDE_USES_ISA_EMULATION li r25,pb5ap /* PB5AP=Peripheral Bank 5 Access Parameters */ mtdcr ebccfga,r25 mtdcr ebccfgd,r4 #endif li r25,pb6ap /* PB6AP=Peripheral Bank 6 Access Parameters */ mtdcr ebccfga,r25 mtdcr ebccfgd,r4 li r25,pb7ap /* PB7AP=Peripheral Bank 7 Access Parameters */ mtdcr ebccfga,r25 mtdcr ebccfgd,r4 li r25,pb2cr /* PB2CR=Peripheral Bank 2 Configuration Register */ mtdcr ebccfga,r25 lis r4,0x780B ori r4,r4,0xA000 mtdcr ebccfgd,r4 /* * the other areas are only 1MiB in size */ lis r4,0x7401 ori r4,r4,0xA000 li r25,pb6cr /* PB6CR=Peripheral Bank 6 Configuration Register */ mtdcr ebccfga,r25 lis r4,0x7401 ori r4,r4,0xA000 mtdcr ebccfgd,r4 li r25,pb7cr /* PB7CR=Peripheral Bank 7 Configuration Register */ mtdcr ebccfga,r25 lis r4,0x7411 ori r4,r4,0xA000 mtdcr ebccfgd,r4 #ifndef CONFIG_ISP1161_PRESENT li r25,pb4cr /* PB4CR=Peripheral Bank 4 Configuration Register */ mtdcr ebccfga,r25 lis r4,0x7421 ori r4,r4,0xA000 mtdcr ebccfgd,r4 #endif #ifdef IDE_USES_ISA_EMULATION li r25,pb5cr /* PB5CR=Peripheral Bank 5 Configuration Register */ mtdcr ebccfga,r25 lis r4,0x0000 ori r4,r4,0x0000 mtdcr ebccfgd,r4 #endif /*----------------------------------------------------------------------- * Memory bank 4: USB controller Philips ISP6111 * 0x77C00000 ... 0x77CFFFFF * * The chip is connected to: * - CPU CS#4 * - CPU IRQ#2 * - CPU DMA 3 * * Timing: * - command to first data: 300ns. Software must ensure this timing! * - Write pulse: 26ns * - Read pulse: 33ns * - read cycle time: 150ns * - write cycle time: 140ns * * Note: All calculations are based on 33MHz EBC clock. One '#' or '_' is 30ns * * |- 300ns --| * |---- 420ns ---|---- 420ns ---| cycle * CS ############:###____#######:###____####### * OE ############:####___#######:####___####### * WE ############:####__########:####__######## * * ----> 2 clocks RD/WR pulses: 60ns * ----> CSN: 3 clock, 90ns * ----> OEN: 1 clocks (read cycle) * ----> WBN: 1 clocks (write cycle) * ----> WBE: 2 clocks * ----> TH: 7 clock, 210ns * ----> TWT: 7 clocks *----------------------------------------------------------------------- */ #ifdef CONFIG_ISP1161_PRESENT li r4,pb4ap /* PB4AP=Peripheral Bank 4 Access Parameters */ mtdcr ebccfga,r4 lis r4,0x030D ori r4,r4,0x5E80 mtdcr ebccfgd,r4 li r4,pb4cr /* PB2CR=Peripheral Bank 4 Configuration Register */ mtdcr ebccfga,r4 lis r4,0x77C1 ori r4,r4,0xA000 mtdcr ebccfgd,r4 #endif #ifndef IDE_USES_ISA_EMULATION /*----------------------------------------------------------------------- * Memory Bank 5 used for IDE access * * Timings for IDE Interface * * SETUP / LENGTH / HOLD - cycles valid for 33.3 MHz clk -> 30ns cycle time * 70 165 30 PIO-Mode 0, [ns] * 3 6 1 [Cycles] ----> AP=0x040C0200 * 50 125 20 PIO-Mode 1, [ns] * 2 5 1 [Cycles] ----> AP=0x03080200 * 30 100 15 PIO-Mode 2, [ns] * 1 4 1 [Cycles] ----> AP=0x02040200 * 30 80 10 PIO-Mode 3, [ns] * 1 3 1 [Cycles] ----> AP=0x01840200 * 25 70 10 PIO-Mode 4, [ns] * 1 3 1 [Cycles] ----> AP=0x01840200 * *----------------------------------------------------------------------- */ li r4,pb5ap mtdcr ebccfga,r4 lis r4,0x040C ori r4,r4,0x0200 mtdcr ebccfgd,r4 li r4,pb5cr /* PB2CR=Peripheral Bank 2 Configuration Register */ mtdcr ebccfga,r4 lis r4,0x7A01 ori r4,r4,0xA000 mtdcr ebccfgd,r4 #endif /* * External Peripheral Control Register */ li r4,epcr mtdcr ebccfga,r4 lis r4,0xB84E ori r4,r4,0xF000 mtdcr ebccfgd,r4 /* * drive POST code */ lis r4,0x7900 ori r4,r4,0x0080 li r3,0x0001 stb r3,0(r4) /* 01 -> external bus controller is initialized */ nop /* pass2 DCR errata #8 */ blr |