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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 | /* * (C) Copyright 2007 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ #include <common.h> #include <asm/timer.h> #include <asm/immap.h> DECLARE_GLOBAL_DATA_PTR; static ulong timestamp; #if defined(CONFIG_SLTTMR) #ifndef CFG_UDELAY_BASE # error "uDelay base not defined!" #endif #if !defined(CFG_TMR_BASE) || !defined(CFG_INTR_BASE) || !defined(CFG_TMRINTR_NO) || !defined(CFG_TMRINTR_MASK) # error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!" #endif extern void dtimer_intr_setup(void); void udelay(unsigned long usec) { volatile slt_t *timerp = (slt_t *) (CFG_UDELAY_BASE); u32 now, freq; /* 1 us period */ freq = CFG_TIMER_PRESCALER; timerp->cr = 0; /* Disable */ timerp->tcnt = usec * freq; timerp->cr = SLT_CR_TEN; now = timerp->cnt; while (now != 0) now = timerp->cnt; timerp->sr |= SLT_SR_ST; timerp->cr = 0; } void dtimer_interrupt(void *not_used) { volatile slt_t *timerp = (slt_t *) (CFG_TMR_BASE); /* check for timer interrupt asserted */ if ((CFG_TMRPND_REG & CFG_TMRINTR_MASK) == CFG_TMRINTR_PEND) { timerp->sr |= SLT_SR_ST; timestamp++; return; } } void timer_init(void) { volatile slt_t *timerp = (slt_t *) (CFG_TMR_BASE); timestamp = 0; timerp->cr = 0; /* disable timer */ timerp->tcnt = 0; timerp->sr = SLT_SR_BE | SLT_SR_ST; /* clear status */ /* initialize and enable timer interrupt */ irq_install_handler(CFG_TMRINTR_NO, dtimer_interrupt, 0); /* Interrupt every ms */ timerp->tcnt = 1000 * CFG_TIMER_PRESCALER; dtimer_intr_setup(); /* set a period of 1us, set timer mode to restart and enable timer and interrupt */ timerp->cr = SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN; } void reset_timer(void) { timestamp = 0; } ulong get_timer(ulong base) { return (timestamp - base); } void set_timer(ulong t) { timestamp = t; } #endif /* CONFIG_SLTTMR */ |