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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 | /* * ColdFire Internal Memory Map and Defines * * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ #ifndef __IMMAP_H #define __IMMAP_H #ifdef CONFIG_M52277 #include <asm/immap_5227x.h> #include <asm/m5227x.h> #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000)) #define CFG_MCFRTC_BASE (MMAP_RTC) #ifdef CONFIG_LCD #define CFG_LCD_BASE (MMAP_LCD) #endif /* Timer */ #ifdef CONFIG_MCFTMR #define CFG_UDELAY_BASE (MMAP_DTMR0) #define CFG_TMR_BASE (MMAP_DTMR1) #define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0) #define CFG_TMRINTR_NO (INT0_HI_DTMR1) #define CFG_TMRINTR_MASK (INTC_IPRH_INT33) #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) #define CFG_TMRINTR_PRI (6) #define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif #ifdef CONFIG_MCFPIT #define CFG_UDELAY_BASE (MMAP_PIT0) #define CFG_PIT_BASE (MMAP_PIT1) #define CFG_PIT_PRESCALE (6) #endif #define CFG_INTR_BASE (MMAP_INTC0) #define CFG_NUM_IRQS (128) #endif /* CONFIG_M52277 */ #ifdef CONFIG_M5235 #include <asm/immap_5235.h> #include <asm/m5235.h> #define CFG_FEC0_IOBASE (MMAP_FEC) #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) /* Timer */ #ifdef CONFIG_MCFTMR #define CFG_UDELAY_BASE (MMAP_DTMR0) #define CFG_TMR_BASE (MMAP_DTMR3) #define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0) #define CFG_TMRINTR_NO (INT0_LO_DTMR3) #define CFG_TMRINTR_MASK (INTC_IPRL_INT22) #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) #define CFG_TMRINTR_PRI (0x1E) /* Level must include inorder to work */ #define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif #ifdef CONFIG_MCFPIT #define CFG_UDELAY_BASE (MMAP_PIT0) #define CFG_PIT_BASE (MMAP_PIT1) #define CFG_PIT_PRESCALE (6) #endif #define CFG_INTR_BASE (MMAP_INTC0) #define CFG_NUM_IRQS (128) #endif /* CONFIG_M5235 */ #ifdef CONFIG_M5249 #include <asm/immap_5249.h> #include <asm/m5249.h> #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) #define CFG_INTR_BASE (MMAP_INTC) #define CFG_NUM_IRQS (64) /* Timer */ #ifdef CONFIG_MCFTMR #define CFG_UDELAY_BASE (MMAP_DTMR0) #define CFG_TMR_BASE (MMAP_DTMR1) #define CFG_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) #define CFG_TMRINTR_NO (31) #define CFG_TMRINTR_MASK (0x00000400) #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) #define CFG_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3) #define CFG_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) #endif #endif /* CONFIG_M5249 */ #ifdef CONFIG_M5253 #include <asm/immap_5253.h> #include <asm/m5249.h> #include <asm/m5253.h> #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) #define CFG_INTR_BASE (MMAP_INTC) #define CFG_NUM_IRQS (64) /* Timer */ #ifdef CONFIG_MCFTMR #define CFG_UDELAY_BASE (MMAP_DTMR0) #define CFG_TMR_BASE (MMAP_DTMR1) #define CFG_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) #define CFG_TMRINTR_NO (27) #define CFG_TMRINTR_MASK (0x00000400) #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) #define CFG_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3) #define CFG_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) #endif #endif /* CONFIG_M5253 */ #ifdef CONFIG_M5271 #include <asm/immap_5271.h> #include <asm/m5271.h> #define CFG_FEC0_IOBASE (MMAP_FEC) #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) /* Timer */ #ifdef CONFIG_MCFTMR #define CFG_UDELAY_BASE (MMAP_DTMR0) #define CFG_TMR_BASE (MMAP_DTMR3) #define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0) #define CFG_TMRINTR_NO (INT0_LO_DTMR3) #define CFG_TMRINTR_MASK (INTC_IPRL_INT22) #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) #define CFG_TMRINTR_PRI (0) /* Level must include inorder to work */ #define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif #define CFG_INTR_BASE (MMAP_INTC0) #define CFG_NUM_IRQS (128) #endif /* CONFIG_M5271 */ #ifdef CONFIG_M5272 #include <asm/immap_5272.h> #include <asm/m5272.h> #define CFG_FEC0_IOBASE (MMAP_FEC) #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) #define CFG_INTR_BASE (MMAP_INTC) #define CFG_NUM_IRQS (64) /* Timer */ #ifdef CONFIG_MCFTMR #define CFG_UDELAY_BASE (MMAP_TMR0) #define CFG_TMR_BASE (MMAP_TMR3) #define CFG_TMRPND_REG (((volatile intctrl_t *)(CFG_INTR_BASE))->int_isr) #define CFG_TMRINTR_NO (INT_TMR3) #define CFG_TMRINTR_MASK (INT_ISR_INT24) #define CFG_TMRINTR_PEND (0) #define CFG_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5)) #define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif #endif /* CONFIG_M5272 */ #ifdef CONFIG_M5282 #include <asm/immap_5282.h> #include <asm/m5282.h> #define CFG_FEC0_IOBASE (MMAP_FEC) #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) #define CFG_INTR_BASE (MMAP_INTC0) #define CFG_NUM_IRQS (128) /* Timer */ #ifdef CONFIG_MCFTMR #define CFG_UDELAY_BASE (MMAP_DTMR0) #define CFG_TMR_BASE (MMAP_DTMR3) #define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0) #define CFG_TMRINTR_NO (INT0_LO_DTMR3) #define CFG_TMRINTR_MASK (1 << INT0_LO_DTMR3) #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) #define CFG_TMRINTR_PRI (0x1E) /* Level must include inorder to work */ #define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif #endif /* CONFIG_M5282 */ #if defined(CONFIG_M5329) || defined(CONFIG_M5373) #include <asm/immap_5329.h> #include <asm/m5329.h> #define CFG_FEC0_IOBASE (MMAP_FEC) #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000)) #define CFG_MCFRTC_BASE (MMAP_RTC) /* Timer */ #ifdef CONFIG_MCFTMR #define CFG_UDELAY_BASE (MMAP_DTMR0) #define CFG_TMR_BASE (MMAP_DTMR1) #define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0) #define CFG_TMRINTR_NO (INT0_HI_DTMR1) #define CFG_TMRINTR_MASK (INTC_IPRH_INT33) #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) #define CFG_TMRINTR_PRI (6) #define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif #ifdef CONFIG_MCFPIT #define CFG_UDELAY_BASE (MMAP_PIT0) #define CFG_PIT_BASE (MMAP_PIT1) #define CFG_PIT_PRESCALE (6) #endif #define CFG_INTR_BASE (MMAP_INTC0) #define CFG_NUM_IRQS (128) #endif /* CONFIG_M5329 && CONFIG_M5373 */ #ifdef CONFIG_M54455 #include <asm/immap_5445x.h> #include <asm/m5445x.h> #define CFG_FEC0_IOBASE (MMAP_FEC0) #define CFG_FEC1_IOBASE (MMAP_FEC1) #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000)) #define CFG_MCFRTC_BASE (MMAP_RTC) /* Timer */ #ifdef CONFIG_MCFTMR #define CFG_UDELAY_BASE (MMAP_DTMR0) #define CFG_TMR_BASE (MMAP_DTMR1) #define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0) #define CFG_TMRINTR_NO (INT0_HI_DTMR1) #define CFG_TMRINTR_MASK (INTC_IPRH_INT33) #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) #define CFG_TMRINTR_PRI (6) #define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif #ifdef CONFIG_MCFPIT #define CFG_UDELAY_BASE (MMAP_PIT0) #define CFG_PIT_BASE (MMAP_PIT1) #define CFG_PIT_PRESCALE (6) #endif #define CFG_INTR_BASE (MMAP_INTC0) #define CFG_NUM_IRQS (128) #ifdef CONFIG_PCI #define CFG_PCI_BAR0 (CFG_MBAR) #define CFG_PCI_BAR5 (CFG_SDRAM_BASE) #define CFG_PCI_TBATR0 (CFG_MBAR) #define CFG_PCI_TBATR5 (CFG_SDRAM_BASE) #endif #endif /* CONFIG_M54455 */ #ifdef CONFIG_M547x #include <asm/immap_547x_8x.h> #include <asm/m547x_8x.h> #ifdef CONFIG_FSLDMAFEC #define CFG_FEC0_IOBASE (MMAP_FEC0) #define CFG_FEC1_IOBASE (MMAP_FEC1) #define FEC0_RX_TASK 0 #define FEC0_TX_TASK 1 #define FEC0_RX_PRIORITY 6 #define FEC0_TX_PRIORITY 7 #define FEC0_RX_INIT 16 #define FEC0_TX_INIT 17 #define FEC1_RX_TASK 2 #define FEC1_TX_TASK 3 #define FEC1_RX_PRIORITY 6 #define FEC1_TX_PRIORITY 7 #define FEC1_RX_INIT 30 #define FEC1_TX_INIT 31 #endif #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x100)) #ifdef CONFIG_SLTTMR #define CFG_UDELAY_BASE (MMAP_SLT1) #define CFG_TMR_BASE (MMAP_SLT0) #define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0) #define CFG_TMRINTR_NO (INT0_HI_SLT0) #define CFG_TMRINTR_MASK (INTC_IPRH_INT54) #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) #define CFG_TMRINTR_PRI (0x1E) #define CFG_TIMER_PRESCALER (gd->bus_clk / 1000000) #endif #define CFG_INTR_BASE (MMAP_INTC0) #define CFG_NUM_IRQS (128) #ifdef CONFIG_PCI #define CFG_PCI_BAR0 (0x40000000) #define CFG_PCI_BAR1 (CFG_SDRAM_BASE) #define CFG_PCI_TBATR0 (CFG_MBAR) #define CFG_PCI_TBATR1 (CFG_SDRAM_BASE) #endif #endif /* CONFIG_M547x */ #ifdef CONFIG_M548x #include <asm/immap_547x_8x.h> #include <asm/m547x_8x.h> #ifdef CONFIG_FSLDMAFEC #define CFG_FEC0_IOBASE (MMAP_FEC0) #define CFG_FEC1_IOBASE (MMAP_FEC1) #define FEC0_RX_TASK 0 #define FEC0_TX_TASK 1 #define FEC0_RX_PRIORITY 6 #define FEC0_TX_PRIORITY 7 #define FEC0_RX_INIT 16 #define FEC0_TX_INIT 17 #define FEC1_RX_TASK 2 #define FEC1_TX_TASK 3 #define FEC1_RX_PRIORITY 6 #define FEC1_TX_PRIORITY 7 #define FEC1_RX_INIT 30 #define FEC1_TX_INIT 31 #endif #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x100)) /* Timer */ #ifdef CONFIG_SLTTMR #define CFG_UDELAY_BASE (MMAP_SLT1) #define CFG_TMR_BASE (MMAP_SLT0) #define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0) #define CFG_TMRINTR_NO (INT0_HI_SLT0) #define CFG_TMRINTR_MASK (INTC_IPRH_INT54) #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) #define CFG_TMRINTR_PRI (0x1E) #define CFG_TIMER_PRESCALER (gd->bus_clk / 1000000) #endif #define CFG_INTR_BASE (MMAP_INTC0) #define CFG_NUM_IRQS (128) #ifdef CONFIG_PCI #define CFG_PCI_BAR0 (CFG_MBAR) #define CFG_PCI_BAR1 (CFG_SDRAM_BASE) #define CFG_PCI_TBATR0 (CFG_MBAR) #define CFG_PCI_TBATR1 (CFG_SDRAM_BASE) #endif #endif /* CONFIG_M548x */ #endif /* __IMMAP_H */ |