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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 | /*----------------------------------------------------------------------------+ | | This source code has been made available to you by IBM on an AS-IS | basis. Anyone receiving this source is licensed under IBM | copyrights to use it in any way he or she deems fit, including | copying it, modifying it, compiling it, and redistributing it either | with or without modifications. No license under IBM patents or | patent applications is to be implied by the copyright license. | | Any user of this software should understand that IBM cannot provide | technical support for this software and will not be responsible for | any consequences resulting from the use of this software. | | Any person who transfers this source code or any derivative work | must include the IBM copyright notice, this paragraph, and the | preceding two paragraphs in the transferred software. | | COPYRIGHT I B M CORPORATION 1999 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M +----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------+ | | File Name: miiphy.h | | Function: Include file defining PHY registers. | | Author: Mark Wisner | +----------------------------------------------------------------------------*/ #ifndef _miiphy_h_ #define _miiphy_h_ #include <net.h> int miiphy_read (char *devname, unsigned char addr, unsigned char reg, unsigned short *value); int miiphy_write (char *devname, unsigned char addr, unsigned char reg, unsigned short value); int miiphy_info (char *devname, unsigned char addr, unsigned int *oui, unsigned char *model, unsigned char *rev); int miiphy_reset (char *devname, unsigned char addr); int miiphy_speed (char *devname, unsigned char addr); int miiphy_duplex (char *devname, unsigned char addr); int miiphy_is_1000base_x (char *devname, unsigned char addr); #ifdef CFG_FAULT_ECHO_LINK_DOWN int miiphy_link (char *devname, unsigned char addr); #endif void miiphy_init (void); void miiphy_register (char *devname, int (*read) (char *devname, unsigned char addr, unsigned char reg, unsigned short *value), int (*write) (char *devname, unsigned char addr, unsigned char reg, unsigned short value)); int miiphy_set_current_dev (char *devname); char *miiphy_get_current_dev (void); void miiphy_listdev (void); #define BB_MII_DEVNAME "bbmii" int bb_miiphy_read (char *devname, unsigned char addr, unsigned char reg, unsigned short *value); int bb_miiphy_write (char *devname, unsigned char addr, unsigned char reg, unsigned short value); /* phy seed setup */ #define AUTO 99 #define _1000BASET 1000 #define _100BASET 100 #define _10BASET 10 #define HALF 22 #define FULL 44 /* phy register offsets */ #define PHY_BMCR 0x00 #define PHY_BMSR 0x01 #define PHY_PHYIDR1 0x02 #define PHY_PHYIDR2 0x03 #define PHY_ANAR 0x04 #define PHY_ANLPAR 0x05 #define PHY_ANER 0x06 #define PHY_ANNPTR 0x07 #define PHY_ANLPNP 0x08 #define PHY_1000BTCR 0x09 #define PHY_1000BTSR 0x0A #define PHY_EXSR 0x0F #define PHY_PHYSTS 0x10 #define PHY_MIPSCR 0x11 #define PHY_MIPGSR 0x12 #define PHY_DCR 0x13 #define PHY_FCSCR 0x14 #define PHY_RECR 0x15 #define PHY_PCSR 0x16 #define PHY_LBR 0x17 #define PHY_10BTSCR 0x18 #define PHY_PHYCTRL 0x19 /* PHY BMCR */ #define PHY_BMCR_RESET 0x8000 #define PHY_BMCR_LOOP 0x4000 #define PHY_BMCR_100MB 0x2000 #define PHY_BMCR_AUTON 0x1000 #define PHY_BMCR_POWD 0x0800 #define PHY_BMCR_ISO 0x0400 #define PHY_BMCR_RST_NEG 0x0200 #define PHY_BMCR_DPLX 0x0100 #define PHY_BMCR_COL_TST 0x0080 #define PHY_BMCR_SPEED_MASK 0x2040 #define PHY_BMCR_1000_MBPS 0x0040 #define PHY_BMCR_100_MBPS 0x2000 #define PHY_BMCR_10_MBPS 0x0000 /* phy BMSR */ #define PHY_BMSR_100T4 0x8000 #define PHY_BMSR_100TXF 0x4000 #define PHY_BMSR_100TXH 0x2000 #define PHY_BMSR_10TF 0x1000 #define PHY_BMSR_10TH 0x0800 #define PHY_BMSR_EXT_STAT 0x0100 #define PHY_BMSR_PRE_SUP 0x0040 #define PHY_BMSR_AUTN_COMP 0x0020 #define PHY_BMSR_RF 0x0010 #define PHY_BMSR_AUTN_ABLE 0x0008 #define PHY_BMSR_LS 0x0004 #define PHY_BMSR_JD 0x0002 #define PHY_BMSR_EXT 0x0001 /*phy ANLPAR */ #define PHY_ANLPAR_NP 0x8000 #define PHY_ANLPAR_ACK 0x4000 #define PHY_ANLPAR_RF 0x2000 #define PHY_ANLPAR_ASYMP 0x0800 #define PHY_ANLPAR_PAUSE 0x0400 #define PHY_ANLPAR_T4 0x0200 #define PHY_ANLPAR_TXFD 0x0100 #define PHY_ANLPAR_TX 0x0080 #define PHY_ANLPAR_10FD 0x0040 #define PHY_ANLPAR_10 0x0020 #define PHY_ANLPAR_100 0x0380 /* we can run at 100 */ /* phy ANLPAR 1000BASE-X */ #define PHY_X_ANLPAR_NP 0x8000 #define PHY_X_ANLPAR_ACK 0x4000 #define PHY_X_ANLPAR_RF_MASK 0x3000 #define PHY_X_ANLPAR_PAUSE_MASK 0x0180 #define PHY_X_ANLPAR_HD 0x0040 #define PHY_X_ANLPAR_FD 0x0020 #define PHY_ANLPAR_PSB_MASK 0x001f #define PHY_ANLPAR_PSB_802_3 0x0001 #define PHY_ANLPAR_PSB_802_9 0x0002 /* phy 1000BTCR */ #define PHY_1000BTCR_1000FD 0x0200 #define PHY_1000BTCR_1000HD 0x0100 /* phy 1000BTSR */ #define PHY_1000BTSR_MSCF 0x8000 #define PHY_1000BTSR_MSCR 0x4000 #define PHY_1000BTSR_LRS 0x2000 #define PHY_1000BTSR_RRS 0x1000 #define PHY_1000BTSR_1000FD 0x0800 #define PHY_1000BTSR_1000HD 0x0400 /* phy EXSR */ #define PHY_EXSR_1000XF 0x8000 #define PHY_EXSR_1000XH 0x4000 #define PHY_EXSR_1000TF 0x2000 #define PHY_EXSR_1000TH 0x1000 #endif |