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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 | /* * (C) Copyright 2007 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * Author: Igor Lisitsin <igor@emcraft.com> * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ #include <config.h> #ifdef CONFIG_POST #include <post.h> #include <ppc_asm.tmpl> #include <ppc_defs.h> #include <asm/cache.h> #include <asm/mmu.h> #if CONFIG_POST & CFG_POST_CACHE .text /* * All 44x variants deal with cache management differently * because they have the address translation always enabled. * The 40x ppc's don't use address translation in U-Boot at all, * so we have to distinguish here between 40x and 44x. */ #ifdef CONFIG_440 /* void cache_post_disable (int tlb) */ cache_post_disable: tlbre r0, r3, 0x0002 ori r0, r0, TLB_WORD2_I_ENABLE@l tlbwe r0, r3, 0x0002 sync isync blr /* void cache_post_wt (int tlb) */ cache_post_wt: tlbre r0, r3, 0x0002 ori r0, r0, TLB_WORD2_W_ENABLE@l andi. r0, r0, ~TLB_WORD2_I_ENABLE@l tlbwe r0, r3, 0x0002 sync isync blr /* void cache_post_wb (int tlb) */ cache_post_wb: tlbre r0, r3, 0x0002 andi. r0, r0, ~TLB_WORD2_W_ENABLE@l andi. r0, r0, ~TLB_WORD2_I_ENABLE@l tlbwe r0, r3, 0x0002 sync isync blr #else /* void cache_post_disable (int tlb) */ cache_post_disable: lis r0, 0x0000 ori r0, r0, 0x0000 mtdccr r0 sync isync blr /* void cache_post_wt (int tlb) */ cache_post_wt: lis r0, 0x8000 ori r0, r0, 0x0000 mtdccr r0 lis r0, 0x8000 ori r0, r0, 0x0000 mtdcwr r0 sync isync blr /* void cache_post_wb (int tlb) */ cache_post_wb: lis r0, 0x8000 ori r0, r0, 0x0000 mtdccr r0 lis r0, 0x0000 ori r0, r0, 0x0000 mtdcwr r0 sync isync blr #endif /* void cache_post_dinvalidate (void *p, int size) */ cache_post_dinvalidate: dcbi r0, r3 addi r3, r3, CFG_CACHELINE_SIZE subic. r4, r4, CFG_CACHELINE_SIZE bgt cache_post_dinvalidate sync blr /* void cache_post_dstore (void *p, int size) */ cache_post_dstore: dcbst r0, r3 addi r3, r3, CFG_CACHELINE_SIZE subic. r4, r4, CFG_CACHELINE_SIZE bgt cache_post_dstore sync blr /* void cache_post_dtouch (void *p, int size) */ cache_post_dtouch: dcbt r0, r3 addi r3, r3, CFG_CACHELINE_SIZE subic. r4, r4, CFG_CACHELINE_SIZE bgt cache_post_dtouch sync blr /* void cache_post_iinvalidate (void) */ cache_post_iinvalidate: iccci r0, r0 sync blr /* void cache_post_memset (void *p, int val, int size) */ cache_post_memset: mtctr r5 1: stb r4, 0(r3) addi r3, r3, 1 bdnz 1b blr /* int cache_post_check (void *p, int size) */ cache_post_check: mtctr r4 1: lbz r0, 0(r3) addi r3, r3, 1 cmpwi r0, 0xff bne 2f bdnz 1b li r3, 0 blr 2: li r3, -1 blr #define CACHE_POST_DISABLE() \ mr r3, r10; \ bl cache_post_disable #define CACHE_POST_WT() \ mr r3, r10; \ bl cache_post_wt #define CACHE_POST_WB() \ mr r3, r10; \ bl cache_post_wb #define CACHE_POST_DINVALIDATE() \ mr r3, r11; \ mr r4, r12; \ bl cache_post_dinvalidate #define CACHE_POST_DFLUSH() \ mr r3, r11; \ mr r4, r12; \ bl cache_post_dflush #define CACHE_POST_DSTORE() \ mr r3, r11; \ mr r4, r12; \ bl cache_post_dstore #define CACHE_POST_DTOUCH() \ mr r3, r11; \ mr r4, r12; \ bl cache_post_dtouch #define CACHE_POST_IINVALIDATE() \ bl cache_post_iinvalidate #define CACHE_POST_MEMSET(val) \ mr r3, r11; \ li r4, val; \ mr r5, r12; \ bl cache_post_memset #define CACHE_POST_CHECK() \ mr r3, r11; \ mr r4, r12; \ bl cache_post_check; \ mr r13, r3 /* * Write and read 0xff pattern with caching enabled. */ .global cache_post_test1 cache_post_test1: mflr r9 mr r10, r3 /* tlb */ mr r11, r4 /* p */ mr r12, r5 /* size */ CACHE_POST_WB() CACHE_POST_DINVALIDATE() /* Write the negative pattern to the test area */ CACHE_POST_MEMSET(0xff) /* Read the test area */ CACHE_POST_CHECK() CACHE_POST_DINVALIDATE() CACHE_POST_DISABLE() mr r3, r13 mtlr r9 blr /* * Write zeroes with caching enabled. * Write 0xff pattern with caching disabled. * Read 0xff pattern with caching enabled. */ .global cache_post_test2 cache_post_test2: mflr r9 mr r10, r3 /* tlb */ mr r11, r4 /* p */ mr r12, r5 /* size */ CACHE_POST_WB() CACHE_POST_DINVALIDATE() /* Write the zero pattern to the test area */ CACHE_POST_MEMSET(0) CACHE_POST_DINVALIDATE() CACHE_POST_DISABLE() /* Write the negative pattern to the test area */ CACHE_POST_MEMSET(0xff) CACHE_POST_WB() /* Read the test area */ CACHE_POST_CHECK() CACHE_POST_DINVALIDATE() CACHE_POST_DISABLE() mr r3, r13 mtlr r9 blr /* * Write-through mode test. * Write zeroes, store the cache, write 0xff pattern. * Invalidate the cache. * Check that 0xff pattern is read. */ .global cache_post_test3 cache_post_test3: mflr r9 mr r10, r3 /* tlb */ mr r11, r4 /* p */ mr r12, r5 /* size */ CACHE_POST_WT() CACHE_POST_DINVALIDATE() /* Cache the test area */ CACHE_POST_DTOUCH() /* Write the zero pattern to the test area */ CACHE_POST_MEMSET(0) CACHE_POST_DSTORE() /* Write the negative pattern to the test area */ CACHE_POST_MEMSET(0xff) CACHE_POST_DINVALIDATE() CACHE_POST_DISABLE() /* Read the test area */ CACHE_POST_CHECK() mr r3, r13 mtlr r9 blr /* * Write-back mode test. * Write 0xff pattern, store the cache, write zeroes. * Invalidate the cache. * Check that 0xff pattern is read. */ .global cache_post_test4 cache_post_test4: mflr r9 mr r10, r3 /* tlb */ mr r11, r4 /* p */ mr r12, r5 /* size */ CACHE_POST_WB() CACHE_POST_DINVALIDATE() /* Cache the test area */ CACHE_POST_DTOUCH() /* Write the negative pattern to the test area */ CACHE_POST_MEMSET(0xff) CACHE_POST_DSTORE() /* Write the zero pattern to the test area */ CACHE_POST_MEMSET(0) CACHE_POST_DINVALIDATE() CACHE_POST_DISABLE() /* Read the test area */ CACHE_POST_CHECK() mr r3, r13 mtlr r9 blr /* * Load the test instructions into the instruction cache. * Replace the test instructions. * Check that the original instructions are executed. */ .global cache_post_test5 cache_post_test5: mflr r9 mr r10, r3 /* tlb */ mr r11, r4 /* p */ mr r12, r5 /* size */ CACHE_POST_WT() CACHE_POST_IINVALIDATE() /* Compute r13 = cache_post_test_inst */ bl cache_post_test5_reloc cache_post_test5_reloc: mflr r13 lis r0, (cache_post_test_inst - cache_post_test5_reloc)@h ori r0, r0, (cache_post_test_inst - cache_post_test5_reloc)@l add r13, r13, r0 /* Copy the test instructions to the test area */ lwz r0, 0(r13) stw r0, 0(r11) lwz r0, 8(r13) stw r0, 4(r11) sync /* Invalidate the cache line */ icbi r0, r11 sync isync /* Execute the test instructions */ mtlr r11 blrl /* Replace the test instruction */ lwz r0, 4(r13) stw r0, 0(r11) sync /* Do not invalidate the cache line */ isync /* Execute the test instructions */ mtlr r11 blrl mr r13, r3 CACHE_POST_IINVALIDATE() CACHE_POST_DINVALIDATE() CACHE_POST_DISABLE() mr r3, r13 mtlr r9 blr /* * Load the test instructions into the instruction cache. * Replace the test instructions and invalidate the cache. * Check that the replaced instructions are executed. */ .global cache_post_test6 cache_post_test6: mflr r9 mr r10, r3 /* tlb */ mr r11, r4 /* p */ mr r12, r5 /* size */ CACHE_POST_WT() CACHE_POST_IINVALIDATE() /* Compute r13 = cache_post_test_inst */ bl cache_post_test6_reloc cache_post_test6_reloc: mflr r13 lis r0, (cache_post_test_inst - cache_post_test6_reloc)@h ori r0, r0, (cache_post_test_inst - cache_post_test6_reloc)@l add r13, r13, r0 /* Copy the test instructions to the test area */ lwz r0, 4(r13) stw r0, 0(r11) lwz r0, 8(r13) stw r0, 4(r11) sync /* Invalidate the cache line */ icbi r0, r11 sync isync /* Execute the test instructions */ mtlr r11 blrl /* Replace the test instruction */ lwz r0, 0(r13) stw r0, 0(r11) sync /* Invalidate the cache line */ icbi r0, r11 sync isync /* Execute the test instructions */ mtlr r11 blrl mr r13, r3 CACHE_POST_IINVALIDATE() CACHE_POST_DINVALIDATE() CACHE_POST_DISABLE() mr r3, r13 mtlr r9 blr /* Test instructions. */ cache_post_test_inst: li r3, 0 li r3, -1 blr #endif /* CONFIG_POST & CFG_POST_CACHE */ #endif /* CONFIG_POST */ |