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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 | /* * (C) Copyright 2007 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * Author: Igor Lisitsin <igor@emcraft.com> * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ #include <common.h> /* * SPR test * * The test checks the contents of Special Purpose Registers (SPR) listed * in the spr_test_list array below. * Each SPR value is read using mfspr instruction, some bits are masked * according to the table and the resulting value is compared to the * corresponding table value. */ #include <post.h> #if CONFIG_POST & CFG_POST_SPR #include <asm/processor.h> #ifdef CONFIG_4xx_DCACHE #include <asm/mmu.h> DECLARE_GLOBAL_DATA_PTR; #endif static struct { int number; char * name; unsigned long mask; unsigned long value; } spr_test_list [] = { /* Standard Special-Purpose Registers */ {0x001, "XER", 0x00000000, 0x00000000}, {0x008, "LR", 0x00000000, 0x00000000}, {0x009, "CTR", 0x00000000, 0x00000000}, {0x016, "DEC", 0x00000000, 0x00000000}, {0x01a, "SRR0", 0x00000000, 0x00000000}, {0x01b, "SRR1", 0x00000000, 0x00000000}, {0x110, "SPRG0", 0x00000000, 0x00000000}, {0x111, "SPRG1", 0x00000000, 0x00000000}, {0x112, "SPRG2", 0x00000000, 0x00000000}, {0x113, "SPRG3", 0x00000000, 0x00000000}, {0x11f, "PVR", 0x00000000, 0x00000000}, /* Additional Special-Purpose Registers. * The values must match the initialization * values from cpu/ppc4xx/start.S */ {0x30, "PID", 0x00000000, 0x00000000}, {0x3a, "CSRR0", 0x00000000, 0x00000000}, {0x3b, "CSRR1", 0x00000000, 0x00000000}, {0x3d, "DEAR", 0x00000000, 0x00000000}, {0x3e, "ESR", 0x00000000, 0x00000000}, {0x3f, "IVPR", 0xffff0000, 0x00000000}, {0x100, "USPRG0", 0x00000000, 0x00000000}, {0x104, "SPRG4", 0x00000000, 0x00000000}, {0x105, "SPRG5", 0x00000000, 0x00000000}, {0x106, "SPRG6", 0x00000000, 0x00000000}, {0x107, "SPRG7", 0x00000000, 0x00000000}, {0x10c, "TBL", 0x00000000, 0x00000000}, {0x10d, "TBU", 0x00000000, 0x00000000}, #ifdef CONFIG_440 {0x11e, "PIR", 0x0000000f, 0x00000000}, #endif {0x130, "DBSR", 0x00000000, 0x00000000}, {0x134, "DBCR0", 0x00000000, 0x00000000}, {0x135, "DBCR1", 0x00000000, 0x00000000}, {0x136, "DBCR2", 0x00000000, 0x00000000}, {0x138, "IAC1", 0x00000000, 0x00000000}, {0x139, "IAC2", 0x00000000, 0x00000000}, {0x13a, "IAC3", 0x00000000, 0x00000000}, {0x13b, "IAC4", 0x00000000, 0x00000000}, {0x13c, "DAC1", 0x00000000, 0x00000000}, {0x13d, "DAC2", 0x00000000, 0x00000000}, {0x13e, "DVC1", 0x00000000, 0x00000000}, {0x13f, "DVC2", 0x00000000, 0x00000000}, {0x150, "TSR", 0x00000000, 0x00000000}, {0x154, "TCR", 0x00000000, 0x00000000}, #ifdef CONFIG_440 {0x190, "IVOR0", 0x0000fff0, 0x00000100}, {0x191, "IVOR1", 0x0000fff0, 0x00000200}, {0x192, "IVOR2", 0x0000fff0, 0x00000300}, {0x193, "IVOR3", 0x0000fff0, 0x00000400}, {0x194, "IVOR4", 0x0000fff0, 0x00000500}, {0x195, "IVOR5", 0x0000fff0, 0x00000600}, {0x196, "IVOR6", 0x0000fff0, 0x00000700}, {0x197, "IVOR7", 0x0000fff0, 0x00000800}, {0x198, "IVOR8", 0x0000fff0, 0x00000c00}, {0x199, "IVOR9", 0x00000000, 0x00000000}, {0x19a, "IVOR10", 0x0000fff0, 0x00000900}, {0x19b, "IVOR11", 0x00000000, 0x00000000}, {0x19c, "IVOR12", 0x00000000, 0x00000000}, {0x19d, "IVOR13", 0x0000fff0, 0x00001300}, {0x19e, "IVOR14", 0x0000fff0, 0x00001400}, {0x19f, "IVOR15", 0x0000fff0, 0x00002000}, #endif {0x23a, "MCSRR0", 0x00000000, 0x00000000}, {0x23b, "MCSRR1", 0x00000000, 0x00000000}, {0x23c, "MCSR", 0x00000000, 0x00000000}, {0x370, "INV0", 0x00000000, 0x00000000}, {0x371, "INV1", 0x00000000, 0x00000000}, {0x372, "INV2", 0x00000000, 0x00000000}, {0x373, "INV3", 0x00000000, 0x00000000}, {0x374, "ITV0", 0x00000000, 0x00000000}, {0x375, "ITV1", 0x00000000, 0x00000000}, {0x376, "ITV2", 0x00000000, 0x00000000}, {0x377, "ITV3", 0x00000000, 0x00000000}, {0x378, "CCR1", 0x00000000, 0x00000000}, {0x390, "DNV0", 0x00000000, 0x00000000}, {0x391, "DNV1", 0x00000000, 0x00000000}, {0x392, "DNV2", 0x00000000, 0x00000000}, {0x393, "DNV3", 0x00000000, 0x00000000}, {0x394, "DTV0", 0x00000000, 0x00000000}, {0x395, "DTV1", 0x00000000, 0x00000000}, {0x396, "DTV2", 0x00000000, 0x00000000}, {0x397, "DTV3", 0x00000000, 0x00000000}, #ifdef CONFIG_440 {0x398, "DVLIM", 0x0fc1f83f, 0x0001f800}, {0x399, "IVLIM", 0x0fc1f83f, 0x0001f800}, #endif {0x39b, "RSTCFG", 0x00000000, 0x00000000}, {0x39c, "DCDBTRL", 0x00000000, 0x00000000}, {0x39d, "DCDBTRH", 0x00000000, 0x00000000}, {0x39e, "ICDBTRL", 0x00000000, 0x00000000}, {0x39f, "ICDBTRH", 0x00000000, 0x00000000}, {0x3b2, "MMUCR", 0x00000000, 0x00000000}, {0x3b3, "CCR0", 0x00000000, 0x00000000}, {0x3d3, "ICDBDR", 0x00000000, 0x00000000}, {0x3f3, "DBDR", 0x00000000, 0x00000000}, }; static int spr_test_list_size = sizeof (spr_test_list) / sizeof (spr_test_list[0]); int spr_post_test (int flags) { int ret = 0; int i; unsigned long code[] = { 0x7c6002a6, /* mfspr r3,SPR */ 0x4e800020 /* blr */ }; unsigned long (*get_spr) (void) = (void *) code; #ifdef CONFIG_4xx_DCACHE /* disable cache */ change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE); #endif for (i = 0; i < spr_test_list_size; i++) { int num = spr_test_list[i].number; /* mfspr r3,num */ code[0] = 0x7c6002a6 | ((num & 0x1F) << 16) | ((num & 0x3E0) << 6); asm volatile ("isync"); if ((get_spr () & spr_test_list[i].mask) != (spr_test_list[i].value & spr_test_list[i].mask)) { post_log ("The value of %s special register " "is incorrect: 0x%08X\n", spr_test_list[i].name, get_spr ()); ret = -1; } } #ifdef CONFIG_4xx_DCACHE /* enable cache */ change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0); #endif return ret; } #endif /* CONFIG_POST & CFG_POST_SPR */ |