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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 | /* * (C) Copyright 2000, 2001 * Rich Ireland, Enterasys Networks, rireland@enterasys.com. * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA * */ /* * FPGA support */ #include <common.h> #include <command.h> #if defined(CONFIG_CMD_NET) #include <net.h> #endif #include <fpga.h> #include <malloc.h> #if 0 #define FPGA_DEBUG #endif #ifdef FPGA_DEBUG #define PRINTF(fmt,args...) printf (fmt ,##args) #else #define PRINTF(fmt,args...) #endif /* Local functions */ static void fpga_usage (cmd_tbl_t * cmdtp); static int fpga_get_op (char *opstr); /* Local defines */ #define FPGA_NONE -1 #define FPGA_INFO 0 #define FPGA_LOAD 1 #define FPGA_LOADB 2 #define FPGA_DUMP 3 #define FPGA_LOADMK 4 /* Convert bitstream data and load into the fpga */ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size) { #if defined(CONFIG_FPGA_XILINX) unsigned int length; unsigned int swapsize; char buffer[80]; unsigned char *dataptr; unsigned int i; int rc; dataptr = (unsigned char *)fpgadata; /* skip the first bytes of the bitsteam, their meaning is unknown */ length = (*dataptr << 8) + *(dataptr+1); dataptr+=2; dataptr+=length; /* get design name (identifier, length, string) */ length = (*dataptr << 8) + *(dataptr+1); dataptr+=2; if (*dataptr++ != 0x61) { PRINTF ("%s: Design name identifier not recognized in bitstream\n", __FUNCTION__ ); return FPGA_FAIL; } length = (*dataptr << 8) + *(dataptr+1); dataptr+=2; for(i=0;i<length;i++) buffer[i] = *dataptr++; printf(" design filename = \"%s\"\n", buffer); /* get part number (identifier, length, string) */ if (*dataptr++ != 0x62) { printf("%s: Part number identifier not recognized in bitstream\n", __FUNCTION__ ); return FPGA_FAIL; } length = (*dataptr << 8) + *(dataptr+1); dataptr+=2; for(i=0;i<length;i++) buffer[i] = *dataptr++; printf(" part number = \"%s\"\n", buffer); /* get date (identifier, length, string) */ if (*dataptr++ != 0x63) { printf("%s: Date identifier not recognized in bitstream\n", __FUNCTION__); return FPGA_FAIL; } length = (*dataptr << 8) + *(dataptr+1); dataptr+=2; for(i=0;i<length;i++) buffer[i] = *dataptr++; printf(" date = \"%s\"\n", buffer); /* get time (identifier, length, string) */ if (*dataptr++ != 0x64) { printf("%s: Time identifier not recognized in bitstream\n",__FUNCTION__); return FPGA_FAIL; } length = (*dataptr << 8) + *(dataptr+1); dataptr+=2; for(i=0;i<length;i++) buffer[i] = *dataptr++; printf(" time = \"%s\"\n", buffer); /* get fpga data length (identifier, length) */ if (*dataptr++ != 0x65) { printf("%s: Data length identifier not recognized in bitstream\n", __FUNCTION__); return FPGA_FAIL; } swapsize = ((unsigned int) *dataptr <<24) + ((unsigned int) *(dataptr+1) <<16) + ((unsigned int) *(dataptr+2) <<8 ) + ((unsigned int) *(dataptr+3) ) ; dataptr+=4; printf(" bytes in bitstream = %d\n", swapsize); rc = fpga_load(dev, dataptr, swapsize); return rc; #else printf("Bitstream support only for Xilinx devices\n"); return FPGA_FAIL; #endif } /* ------------------------------------------------------------------------- */ /* command form: * fpga <op> <device number> <data addr> <datasize> * where op is 'load', 'dump', or 'info' * If there is no device number field, the fpga environment variable is used. * If there is no data addr field, the fpgadata environment variable is used. * The info command requires no data address field. */ int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { int op, dev = FPGA_INVALID_DEVICE; size_t data_size = 0; void *fpga_data = NULL; char *devstr = getenv ("fpga"); char *datastr = getenv ("fpgadata"); int rc = FPGA_FAIL; #if defined (CONFIG_FIT) const char *fit_uname = NULL; ulong fit_addr; #endif if (devstr) dev = (int) simple_strtoul (devstr, NULL, 16); if (datastr) fpga_data = (void *) simple_strtoul (datastr, NULL, 16); switch (argc) { case 5: /* fpga <op> <dev> <data> <datasize> */ data_size = simple_strtoul (argv[4], NULL, 16); case 4: /* fpga <op> <dev> <data> */ #if defined(CONFIG_FIT) if (fit_parse_subimage (argv[3], (ulong)fpga_data, &fit_addr, &fit_uname)) { fpga_data = (void *)fit_addr; debug ("* fpga: subimage '%s' from FIT image at 0x%08lx\n", fit_uname, fit_addr); } else #endif { fpga_data = (void *) simple_strtoul (argv[3], NULL, 16); debug ("* fpga: cmdline image address = 0x%08lx\n", (ulong)fpga_data); } PRINTF ("%s: fpga_data = 0x%x\n", __FUNCTION__, (uint) fpga_data); case 3: /* fpga <op> <dev | data addr> */ dev = (int) simple_strtoul (argv[2], NULL, 16); PRINTF ("%s: device = %d\n", __FUNCTION__, dev); /* FIXME - this is a really weak test */ if ((argc == 3) && (dev > fpga_count ())) { /* must be buffer ptr */ PRINTF ("%s: Assuming buffer pointer in arg 3\n", __FUNCTION__); #if defined(CONFIG_FIT) if (fit_parse_subimage (argv[2], (ulong)fpga_data, &fit_addr, &fit_uname)) { fpga_data = (void *)fit_addr; debug ("* fpga: subimage '%s' from FIT image at 0x%08lx\n", fit_uname, fit_addr); } else #endif { fpga_data = (void *) dev; debug ("* fpga: cmdline image address = 0x%08lx\n", (ulong)fpga_data); } PRINTF ("%s: fpga_data = 0x%x\n", __FUNCTION__, (uint) fpga_data); dev = FPGA_INVALID_DEVICE; /* reset device num */ } case 2: /* fpga <op> */ op = (int) fpga_get_op (argv[1]); break; default: PRINTF ("%s: Too many or too few args (%d)\n", __FUNCTION__, argc); op = FPGA_NONE; /* force usage display */ break; } switch (op) { case FPGA_NONE: fpga_usage (cmdtp); break; case FPGA_INFO: rc = fpga_info (dev); break; case FPGA_LOAD: rc = fpga_load (dev, fpga_data, data_size); break; case FPGA_LOADB: rc = fpga_loadbitstream(dev, fpga_data, data_size); break; case FPGA_LOADMK: switch (genimg_get_format (fpga_data)) { case IMAGE_FORMAT_LEGACY: { image_header_t *hdr = (image_header_t *)fpga_data; ulong data; data = (ulong)image_get_data (hdr); data_size = image_get_data_size (hdr); rc = fpga_load (dev, (void *)data, data_size); } break; #if defined(CONFIG_FIT) case IMAGE_FORMAT_FIT: { const void *fit_hdr = (const void *)fpga_data; int noffset; void *fit_data; if (fit_uname == NULL) { puts ("No FIT subimage unit name\n"); return 1; } if (!fit_check_format (fit_hdr)) { puts ("Bad FIT image format\n"); return 1; } /* get fpga component image node offset */ noffset = fit_image_get_node (fit_hdr, fit_uname); if (noffset < 0) { printf ("Can't find '%s' FIT subimage\n", fit_uname); return 1; } /* verify integrity */ if (!fit_image_check_hashes (fit_hdr, noffset)) { puts ("Bad Data Hash\n"); return 1; } /* get fpga subimage data address and length */ if (fit_image_get_data (fit_hdr, noffset, &fit_data, &data_size)) { puts ("Could not find fpga subimage data\n"); return 1; } rc = fpga_load (dev, fit_data, data_size); } break; #endif default: puts ("** Unknown image type\n"); rc = FPGA_FAIL; break; } break; case FPGA_DUMP: rc = fpga_dump (dev, fpga_data, data_size); break; default: printf ("Unknown operation\n"); fpga_usage (cmdtp); break; } return (rc); } static void fpga_usage (cmd_tbl_t * cmdtp) { printf ("Usage:\n%s\n", cmdtp->usage); } /* * Map op to supported operations. We don't use a table since we * would just have to relocate it from flash anyway. */ static int fpga_get_op (char *opstr) { int op = FPGA_NONE; if (!strcmp ("info", opstr)) { op = FPGA_INFO; } else if (!strcmp ("loadb", opstr)) { op = FPGA_LOADB; } else if (!strcmp ("load", opstr)) { op = FPGA_LOAD; } else if (!strcmp ("loadmk", opstr)) { op = FPGA_LOADMK; } else if (!strcmp ("dump", opstr)) { op = FPGA_DUMP; } if (op == FPGA_NONE) { printf ("Unknown fpga operation \"%s\"\n", opstr); } return op; } U_BOOT_CMD (fpga, 6, 1, do_fpga, "fpga - loadable FPGA image support\n", "fpga [operation type] [device number] [image address] [image size]\n" "fpga operations:\n" "\tinfo\tlist known device information\n" "\tload\tLoad device from memory buffer\n" "\tloadb\tLoad device from bitstream buffer (Xilinx devices only)\n" "\tloadmk\tLoad device generated with mkimage\n" "\tdump\tLoad device to memory buffer\n" #if defined(CONFIG_FIT) "\tFor loadmk operating on FIT format uImage address must include\n" "\tsubimage unit name in the form of addr:<subimg_uname>\n" #endif ); |