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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 | #include <config.h> #include <mpc86xx.h> #include <version.h> #include <ppc_asm.tmpl> #include <ppc_defs.h> #include <asm/cache.h> #include <asm/mmu.h> #ifndef CACHE_LINE_SIZE # define CACHE_LINE_SIZE L1_CACHE_BYTES #endif #if CACHE_LINE_SIZE == 128 #define LG_CACHE_LINE_SIZE 7 #elif CACHE_LINE_SIZE == 32 #define LG_CACHE_LINE_SIZE 5 #elif CACHE_LINE_SIZE == 16 #define LG_CACHE_LINE_SIZE 4 #elif CACHE_LINE_SIZE == 8 #define LG_CACHE_LINE_SIZE 3 #else # error "Invalid cache line size!" #endif /* * Most of this code is taken from 74xx_7xx/cache.S * and then cleaned up a bit */ /* * Invalidate L1 instruction cache. */ _GLOBAL(invalidate_l1_instruction_cache) /* use invalidate-all bit in HID0 */ mfspr r3,HID0 ori r3,r3,HID0_ICFI mtspr HID0,r3 isync blr /* * Invalidate L1 data cache. */ _GLOBAL(invalidate_l1_data_cache) mfspr r3,HID0 ori r3,r3,HID0_DCFI mtspr HID0,r3 isync blr /* * Flush data cache. */ _GLOBAL(flush_data_cache) lis r3,0 lis r5,CACHE_LINE_SIZE flush: cmp 0,1,r3,r5 bge done lwz r5,0(r3) lis r5,CACHE_LINE_SIZE addi r3,r3,0x4 b flush done: blr /* * Write any modified data cache blocks out to memory * and invalidate the corresponding instruction cache blocks. * This is a no-op on the 601. * * flush_icache_range(unsigned long start, unsigned long stop) */ _GLOBAL(flush_icache_range) li r5,CACHE_LINE_SIZE-1 andc r3,r3,r5 subf r4,r3,r4 add r4,r4,r5 srwi. r4,r4,LG_CACHE_LINE_SIZE beqlr mtctr r4 mr r6,r3 1: dcbst 0,r3 addi r3,r3,CACHE_LINE_SIZE bdnz 1b sync /* wait for dcbst's to get to ram */ mtctr r4 2: icbi 0,r6 addi r6,r6,CACHE_LINE_SIZE bdnz 2b sync /* additional sync needed on g4 */ isync blr /* * Write any modified data cache blocks out to memory. * Does not invalidate the corresponding cache lines (especially for * any corresponding instruction cache). * * clean_dcache_range(unsigned long start, unsigned long stop) */ _GLOBAL(clean_dcache_range) li r5,CACHE_LINE_SIZE-1 andc r3,r3,r5 /* align r3 down to cache line */ subf r4,r3,r4 /* r4 = offset of stop from start of cache line */ add r4,r4,r5 /* r4 += cache_line_size-1 */ srwi. r4,r4,LG_CACHE_LINE_SIZE /* r4 = number of cache lines to flush */ beqlr /* if r4 == 0 return */ mtctr r4 /* ctr = r4 */ sync 1: dcbst 0,r3 addi r3,r3,CACHE_LINE_SIZE bdnz 1b sync /* wait for dcbst's to get to ram */ blr /* * Write any modified data cache blocks out to memory * and invalidate the corresponding instruction cache blocks. * * flush_dcache_range(unsigned long start, unsigned long stop) */ _GLOBAL(flush_dcache_range) li r5,CACHE_LINE_SIZE-1 andc r3,r3,r5 subf r4,r3,r4 add r4,r4,r5 srwi. r4,r4,LG_CACHE_LINE_SIZE beqlr mtctr r4 sync 1: dcbf 0,r3 addi r3,r3,CACHE_LINE_SIZE bdnz 1b sync /* wait for dcbf's to get to ram */ blr /* * Like above, but invalidate the D-cache. This is used by the 8xx * to invalidate the cache so the PPC core doesn't get stale data * from the CPM (no cache snooping here :-). * * invalidate_dcache_range(unsigned long start, unsigned long stop) */ _GLOBAL(invalidate_dcache_range) li r5,CACHE_LINE_SIZE-1 andc r3,r3,r5 subf r4,r3,r4 add r4,r4,r5 srwi. r4,r4,LG_CACHE_LINE_SIZE beqlr mtctr r4 sync 1: dcbi 0,r3 addi r3,r3,CACHE_LINE_SIZE bdnz 1b sync /* wait for dcbi's to get to ram */ blr /* * Flush a particular page from the data cache to RAM. * Note: this is necessary because the instruction cache does *not* * snoop from the data cache. * * void __flush_page_to_ram(void *page) */ _GLOBAL(__flush_page_to_ram) rlwinm r3,r3,0,0,19 /* Get page base address */ li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */ mtctr r4 mr r6,r3 0: dcbst 0,r3 /* Write line to ram */ addi r3,r3,CACHE_LINE_SIZE bdnz 0b sync mtctr r4 1: icbi 0,r6 addi r6,r6,CACHE_LINE_SIZE bdnz 1b sync isync blr /* * Flush a particular page from the instruction cache. * Note: this is necessary because the instruction cache does *not* * snoop from the data cache. * * void __flush_icache_page(void *page) */ _GLOBAL(__flush_icache_page) li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */ mtctr r4 1: icbi 0,r3 addi r3,r3,CACHE_LINE_SIZE bdnz 1b sync isync blr /* * Clear a page using the dcbz instruction, which doesn't cause any * memory traffic (except to write out any cache lines which get * displaced). This only works on cacheable memory. */ _GLOBAL(clear_page) li r0,4096/CACHE_LINE_SIZE mtctr r0 1: dcbz 0,r3 addi r3,r3,CACHE_LINE_SIZE bdnz 1b blr /* * Enable L1 Instruction cache */ _GLOBAL(icache_enable) mfspr r3, HID0 li r5, HID0_ICFI|HID0_ILOCK andc r3, r3, r5 ori r3, r3, HID0_ICE ori r5, r3, HID0_ICFI mtspr HID0, r5 mtspr HID0, r3 isync blr /* * Disable L1 Instruction cache */ _GLOBAL(icache_disable) mfspr r3, HID0 li r5, 0 ori r5, r5, HID0_ICE andc r3, r3, r5 mtspr HID0, r3 isync blr /* * Is instruction cache enabled? */ _GLOBAL(icache_status) mfspr r3, HID0 andi. r3, r3, HID0_ICE blr _GLOBAL(l1dcache_enable) mfspr r3, HID0 li r5, HID0_DCFI|HID0_DLOCK andc r3, r3, r5 mtspr HID0, r3 /* no invalidate, unlock */ ori r3, r3, HID0_DCE ori r5, r3, HID0_DCFI mtspr HID0, r5 /* enable + invalidate */ mtspr HID0, r3 /* enable */ sync blr /* * Enable data cache(s) - L1 and optionally L2 * Calls l2cache_enable. LR saved in r5 */ _GLOBAL(dcache_enable) mfspr r3, HID0 li r5, HID0_DCFI|HID0_DLOCK andc r3, r3, r5 mtspr HID0, r3 /* no invalidate, unlock */ ori r3, r3, HID0_DCE ori r5, r3, HID0_DCFI mtspr HID0, r5 /* enable + invalidate */ mtspr HID0, r3 /* enable */ sync #ifdef CFG_L2 mflr r5 bl l2cache_enable /* uses r3 and r4 */ sync mtlr r5 #endif blr /* * Disable data cache(s) - L1 and optionally L2 * Calls flush_data_cache and l2cache_disable_no_flush. * LR saved in r4 */ _GLOBAL(dcache_disable) mflr r4 /* save link register */ bl flush_data_cache /* uses r3 and r5 */ sync mfspr r3, HID0 li r5, HID0_DCFI|HID0_DLOCK andc r3, r3, r5 mtspr HID0, r3 /* no invalidate, unlock */ li r5, HID0_DCE|HID0_DCFI andc r3, r3, r5 /* no enable, no invalidate */ mtspr HID0, r3 sync #ifdef CFG_L2 bl l2cache_disable_no_flush /* uses r3 */ #endif mtlr r4 /* restore link register */ blr /* * Is data cache enabled? */ _GLOBAL(dcache_status) mfspr r3, HID0 andi. r3, r3, HID0_DCE blr /* * Invalidate L2 cache using L2I, assume L2 is enabled */ _GLOBAL(l2cache_invalidate) mfspr r3, l2cr rlwinm. r3, r3, 0, 0, 0 beq 1f mfspr r3, l2cr rlwinm r3, r3, 0, 1, 31 #ifdef CONFIG_ALTIVEC dssall #endif sync mtspr l2cr, r3 sync 1: mfspr r3, l2cr oris r3, r3, L2CR_L2I@h mtspr l2cr, r3 invl2: mfspr r3, l2cr andis. r3, r3, L2CR_L2I@h bne invl2 blr /* * Enable L2 cache * Calls l2cache_invalidate. LR is saved in r4 */ _GLOBAL(l2cache_enable) mflr r4 /* save link register */ bl l2cache_invalidate /* uses r3 */ sync lis r3, L2_ENABLE@h ori r3, r3, L2_ENABLE@l mtspr l2cr, r3 isync mtlr r4 /* restore link register */ blr /* * Disable L2 cache * Calls flush_data_cache. LR is saved in r4 */ _GLOBAL(l2cache_disable) mflr r4 /* save link register */ bl flush_data_cache /* uses r3 and r5 */ sync mtlr r4 /* restore link register */ l2cache_disable_no_flush: /* provide way to disable L2 w/o flushing */ lis r3, L2_INIT@h ori r3, r3, L2_INIT@l mtspr l2cr, r3 isync blr |