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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 | menu "RISC-V architecture" depends on RISCV config SYS_ARCH default "riscv" choice prompt "Target select" optional config TARGET_AX25_AE350 bool "Support ax25-ae350" config TARGET_MICROCHIP_ICICLE bool "Support Microchip PolarFire-SoC Icicle Board" config TARGET_QEMU_VIRT bool "Support QEMU Virt Board" config TARGET_SIFIVE_FU540 bool "Support SiFive FU540 Board" endchoice config SYS_ICACHE_OFF bool "Do not enable icache" default n help Do not enable instruction cache in U-Boot. config SPL_SYS_ICACHE_OFF bool "Do not enable icache in SPL" depends on SPL default SYS_ICACHE_OFF help Do not enable instruction cache in SPL. config SYS_DCACHE_OFF bool "Do not enable dcache" default n help Do not enable data cache in U-Boot. config SPL_SYS_DCACHE_OFF bool "Do not enable dcache in SPL" depends on SPL default SYS_DCACHE_OFF help Do not enable data cache in SPL. # board-specific options below source "board/AndesTech/ax25-ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_icicle/Kconfig" source "board/sifive/fu540/Kconfig" # platform-specific options below source "arch/riscv/cpu/ax25/Kconfig" source "arch/riscv/cpu/generic/Kconfig" # architecture-specific options below choice prompt "Base ISA" default ARCH_RV32I config ARCH_RV32I bool "RV32I" select 32BIT help Choose this option to target the RV32I base integer instruction set. config ARCH_RV64I bool "RV64I" select 64BIT select PHYS_64BIT help Choose this option to target the RV64I base integer instruction set. endchoice choice prompt "Code Model" default CMODEL_MEDLOW config CMODEL_MEDLOW bool "medium low code model" help U-Boot and its statically defined symbols must lie within a single 2 GiB address range and must lie between absolute addresses -2 GiB and +2 GiB. config CMODEL_MEDANY bool "medium any code model" help U-Boot and its statically defined symbols must be within any single 2 GiB address range. endchoice choice prompt "Run Mode" default RISCV_MMODE config RISCV_MMODE bool "Machine" help Choose this option to build U-Boot for RISC-V M-Mode. config RISCV_SMODE bool "Supervisor" help Choose this option to build U-Boot for RISC-V S-Mode. endchoice choice prompt "SPL Run Mode" default SPL_RISCV_MMODE depends on SPL config SPL_RISCV_MMODE bool "Machine" help Choose this option to build U-Boot SPL for RISC-V M-Mode. config SPL_RISCV_SMODE bool "Supervisor" help Choose this option to build U-Boot SPL for RISC-V S-Mode. endchoice config RISCV_ISA_C bool "Emit compressed instructions" default y help Adds "C" to the ISA subsets that the toolchain is allowed to emit when building U-Boot, which results in compressed instructions in the U-Boot binary. config RISCV_ISA_A def_bool y config 32BIT bool config 64BIT bool config SIFIVE_CLINT bool depends on RISCV_MMODE || SPL_RISCV_MMODE select REGMAP select SYSCON select SPL_REGMAP if SPL select SPL_SYSCON if SPL help The SiFive CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. config ANDES_PLIC bool depends on RISCV_MMODE || SPL_RISCV_MMODE select REGMAP select SYSCON select SPL_REGMAP if SPL select SPL_SYSCON if SPL help The Andes PLIC block holds memory-mapped claim and pending registers associated with software interrupt. config ANDES_PLMT bool depends on RISCV_MMODE || SPL_RISCV_MMODE select REGMAP select SYSCON select SPL_REGMAP if SPL select SPL_SYSCON if SPL help The Andes PLMT block holds memory-mapped mtime register associated with timer tick. config RISCV_RDTIME bool default y if RISCV_SMODE || SPL_RISCV_SMODE help The provides the riscv_get_time() API that is implemented using the standard rdtime instruction. This is the case for S-mode U-Boot, and is useful for processors that support rdtime in M-mode too. config SYS_MALLOC_F_LEN default 0x1000 config SMP bool "Symmetric Multi-Processing" help This enables support for systems with more than one CPU. If you say N here, U-Boot will run on single and multiprocessor machines, but will use only one CPU of a multiprocessor machine. If you say Y here, U-Boot will run on many, but not all, single processor machines. config NR_CPUS int "Maximum number of CPUs (2-32)" range 2 32 depends on SMP default 8 help On multiprocessor machines, U-Boot sets up a stack for each CPU. Stack memory is pre-allocated. U-Boot must therefore know the maximum number of CPUs that may be present. config SBI_IPI bool default y if RISCV_SMODE || SPL_RISCV_SMODE depends on SMP config XIP bool "XIP mode" help XIP (eXecute In Place) is a method for executing code directly from a NOR flash memory without copying the code to ram. Say yes here if U-Boot boots from flash directly. config STACK_SIZE_SHIFT int default 14 config SPL_LDSCRIPT default "arch/riscv/cpu/u-boot-spl.lds" endmenu |