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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 | // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> */ #include <common.h> #include <acpi_s3.h> #include <cpu_func.h> #include <dm.h> #include <errno.h> #include <rtc.h> #include <asm/cmos_layout.h> #include <asm/early_cmos.h> #include <asm/io.h> #include <asm/mrccache.h> #include <asm/post.h> #include <asm/processor.h> #include <asm/fsp/fsp_support.h> DECLARE_GLOBAL_DATA_PTR; int checkcpu(void) { return 0; } int print_cpuinfo(void) { post_code(POST_CPU_INFO); return default_print_cpuinfo(); } int fsp_init_phase_pci(void) { u32 status; /* call into FspNotify */ debug("Calling into FSP (notify phase INIT_PHASE_PCI): "); status = fsp_notify(NULL, INIT_PHASE_PCI); if (status) debug("fail, error code %x\n", status); else debug("OK\n"); return status ? -EPERM : 0; } void board_final_cleanup(void) { u32 status; /* call into FspNotify */ debug("Calling into FSP (notify phase INIT_PHASE_BOOT): "); status = fsp_notify(NULL, INIT_PHASE_BOOT); if (status) debug("fail, error code %x\n", status); else debug("OK\n"); } void *fsp_prepare_mrc_cache(void) { struct mrc_data_container *cache; struct mrc_region entry; int ret; ret = mrccache_get_region(NULL, &entry); if (ret) return NULL; cache = mrccache_find_current(&entry); if (!cache) return NULL; debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__, cache->data, cache->data_size, cache->checksum); return cache->data; } #ifdef CONFIG_HAVE_ACPI_RESUME int fsp_save_s3_stack(void) { struct udevice *dev; int ret; if (gd->arch.prev_sleep_state == ACPI_S3) return 0; ret = uclass_get_device(UCLASS_RTC, 0, &dev); if (ret) { debug("Cannot find RTC: err=%d\n", ret); return -ENODEV; } /* Save the stack address to CMOS */ ret = rtc_write32(dev, CMOS_FSP_STACK_ADDR, gd->start_addr_sp); if (ret) { debug("Save stack address to CMOS: err=%d\n", ret); return -EIO; } return 0; } #endif |