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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 | // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ #define LOG_CATEGORY UCLASS_RESET #include <common.h> #include <dm.h> #include <errno.h> #include <log.h> #include <malloc.h> #include <reset-uclass.h> #include <stm32_rcc.h> #include <asm/io.h> #include <dm/device_compat.h> #include <linux/bitops.h> /* offset of register without set/clear management */ #define RCC_MP_GCR_OFFSET 0x10C /* reset clear offset for STM32MP RCC */ #define RCC_CL 0x4 struct stm32_reset_priv { fdt_addr_t base; }; static int stm32_reset_request(struct reset_ctl *reset_ctl) { return 0; } static int stm32_reset_free(struct reset_ctl *reset_ctl) { return 0; } static int stm32_reset_assert(struct reset_ctl *reset_ctl) { struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev); int bank = (reset_ctl->id / (sizeof(u32) * BITS_PER_BYTE)) * 4; int offset = reset_ctl->id % (sizeof(u32) * BITS_PER_BYTE); dev_dbg(reset_ctl->dev, "reset id = %ld bank = %d offset = %d)\n", reset_ctl->id, bank, offset); if (dev_get_driver_data(reset_ctl->dev) == STM32MP1) if (bank != RCC_MP_GCR_OFFSET) /* reset assert is done in rcc set register */ writel(BIT(offset), priv->base + bank); else clrbits_le32(priv->base + bank, BIT(offset)); else setbits_le32(priv->base + bank, BIT(offset)); return 0; } static int stm32_reset_deassert(struct reset_ctl *reset_ctl) { struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev); int bank = (reset_ctl->id / (sizeof(u32) * BITS_PER_BYTE)) * 4; int offset = reset_ctl->id % (sizeof(u32) * BITS_PER_BYTE); dev_dbg(reset_ctl->dev, "reset id = %ld bank = %d offset = %d)\n", reset_ctl->id, bank, offset); if (dev_get_driver_data(reset_ctl->dev) == STM32MP1) if (bank != RCC_MP_GCR_OFFSET) /* reset deassert is done in rcc clr register */ writel(BIT(offset), priv->base + bank + RCC_CL); else setbits_le32(priv->base + bank, BIT(offset)); else clrbits_le32(priv->base + bank, BIT(offset)); return 0; } static const struct reset_ops stm32_reset_ops = { .request = stm32_reset_request, .rfree = stm32_reset_free, .rst_assert = stm32_reset_assert, .rst_deassert = stm32_reset_deassert, }; static int stm32_reset_probe(struct udevice *dev) { struct stm32_reset_priv *priv = dev_get_priv(dev); priv->base = dev_read_addr(dev); if (priv->base == FDT_ADDR_T_NONE) { /* for MFD, get address of parent */ priv->base = dev_read_addr(dev->parent); if (priv->base == FDT_ADDR_T_NONE) return -EINVAL; } return 0; } U_BOOT_DRIVER(stm32_rcc_reset) = { .name = "stm32_rcc_reset", .id = UCLASS_RESET, .probe = stm32_reset_probe, .priv_auto = sizeof(struct stm32_reset_priv), .ops = &stm32_reset_ops, }; |