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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 | // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2022 StarFive Technology Co., Ltd. * Author: Yanhong Wang<yanhong.wang@starfivetech.com> */ #include <common.h> #include <asm/arch/eeprom.h> #include <asm/arch/gpio.h> #include <asm/arch/regs.h> #include <asm/arch/spl.h> #include <asm/io.h> #include <dt-bindings/clock/starfive,jh7110-crg.h> #include <fdt_support.h> #include <linux/libfdt.h> #include <log.h> #include <spl.h> DECLARE_GLOBAL_DATA_PTR; #define JH7110_CLK_CPU_ROOT_OFFSET 0x0U #define JH7110_CLK_CPU_ROOT_SHIFT 24 #define JH7110_CLK_CPU_ROOT_MASK GENMASK(29, 24) struct starfive_vf2_pro { const char *path; const char *name; const char *value; }; static const struct starfive_vf2_pro starfive_vera[] = { {"/soc/ethernet@16030000/mdio/ethernet-phy@0", "rx-internal-delay-ps", "1900"}, {"/soc/ethernet@16030000/mdio/ethernet-phy@0", "tx-internal-delay-ps", "1350"} }; static const struct starfive_vf2_pro starfive_verb[] = { {"/soc/ethernet@16030000", "starfive,tx-use-rgmii-clk", NULL}, {"/soc/ethernet@16040000", "starfive,tx-use-rgmii-clk", NULL}, {"/soc/ethernet@16030000/mdio/ethernet-phy@0", "motorcomm,tx-clk-adj-enabled", NULL}, {"/soc/ethernet@16030000/mdio/ethernet-phy@0", "motorcomm,tx-clk-100-inverted", NULL}, {"/soc/ethernet@16030000/mdio/ethernet-phy@0", "motorcomm,tx-clk-1000-inverted", NULL}, {"/soc/ethernet@16030000/mdio/ethernet-phy@0", "rx-internal-delay-ps", "1900"}, {"/soc/ethernet@16030000/mdio/ethernet-phy@0", "tx-internal-delay-ps", "1500"}, {"/soc/ethernet@16040000/mdio/ethernet-phy@1", "motorcomm,tx-clk-adj-enabled", NULL}, { "/soc/ethernet@16040000/mdio/ethernet-phy@1", "motorcomm,tx-clk-100-inverted", NULL}, {"/soc/ethernet@16040000/mdio/ethernet-phy@1", "rx-internal-delay-ps", "0"}, {"/soc/ethernet@16040000/mdio/ethernet-phy@1", "tx-internal-delay-ps", "0"}, }; void spl_fdt_fixup_version_a(void *fdt) { u32 phandle; u8 i; int offset; int ret; fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", "StarFive VisionFive 2 v1.2A"); offset = fdt_path_offset(fdt, "/soc/clock-controller@13020000"); phandle = fdt_get_phandle(fdt, offset); offset = fdt_path_offset(fdt, "/soc/ethernet@16040000"); fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX); fdt_appendprop_u32(fdt, offset, "assigned-clocks", phandle); fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_RX); fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", JH7110_SYSCLK_GMAC1_RMII_RTX); fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", phandle); fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", JH7110_SYSCLK_GMAC1_RMII_RTX); fdt_setprop_string(fdt, fdt_path_offset(fdt, "/soc/ethernet@16040000"), "phy-mode", "rmii"); for (i = 0; i < ARRAY_SIZE(starfive_vera); i++) { offset = fdt_path_offset(fdt, starfive_vera[i].path); if (starfive_vera[i].value) ret = fdt_setprop_u32(fdt, offset, starfive_vera[i].name, dectoul(starfive_vera[i].value, NULL)); else ret = fdt_setprop_empty(fdt, offset, starfive_vera[i].name); if (ret) { pr_err("%s set prop %s fail.\n", __func__, starfive_vera[i].name); break; } } } void spl_fdt_fixup_version_b(void *fdt) { u32 phandle; u8 i; int offset; int ret; fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", "StarFive VisionFive 2 v1.3B"); /* gmac0 */ offset = fdt_path_offset(fdt, "/soc/clock-controller@17000000"); phandle = fdt_get_phandle(fdt, offset); offset = fdt_path_offset(fdt, "/soc/ethernet@16030000"); fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX); fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", JH7110_AONCLK_GMAC0_RMII_RTX); /* gmac1 */ offset = fdt_path_offset(fdt, "/soc/clock-controller@13020000"); phandle = fdt_get_phandle(fdt, offset); offset = fdt_path_offset(fdt, "/soc/ethernet@16040000"); fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX); fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", JH7110_SYSCLK_GMAC1_RMII_RTX); for (i = 0; i < ARRAY_SIZE(starfive_verb); i++) { offset = fdt_path_offset(fdt, starfive_verb[i].path); if (starfive_verb[i].value) ret = fdt_setprop_u32(fdt, offset, starfive_verb[i].name, dectoul(starfive_verb[i].value, NULL)); else ret = fdt_setprop_empty(fdt, offset, starfive_verb[i].name); if (ret) { pr_err("%s set prop %s fail.\n", __func__, starfive_verb[i].name); break; } } } void spl_perform_fixups(struct spl_image_info *spl_image) { u8 version; version = get_pcb_revision_from_eeprom(); switch (version) { case 'a': case 'A': spl_fdt_fixup_version_a(spl_image->fdt_addr); break; case 'b': case 'B': default: spl_fdt_fixup_version_b(spl_image->fdt_addr); break; }; /* Update the memory size which read form eeprom or DT */ fdt_fixup_memory(spl_image->fdt_addr, 0x40000000, gd->ram_size); } static void jh7110_jtag_init(void) { /* nTRST: GPIO36 */ SYS_IOMUX_DOEN(36, HIGH); SYS_IOMUX_DIN(36, 4); /* TDI: GPIO61 */ SYS_IOMUX_DOEN(61, HIGH); SYS_IOMUX_DIN(61, 19); /* TMS: GPIO63 */ SYS_IOMUX_DOEN(63, HIGH); SYS_IOMUX_DIN(63, 20); /* TCK: GPIO60 */ SYS_IOMUX_DOEN(60, HIGH); SYS_IOMUX_DIN(60, 29); /* TDO: GPIO44 */ SYS_IOMUX_DOEN(44, 8); SYS_IOMUX_DOUT(44, 22); } int spl_board_init_f(void) { int ret; jh7110_jtag_init(); ret = spl_soc_init(); if (ret) { debug("JH7110 SPL init failed: %d\n", ret); return ret; } return 0; } u32 spl_boot_device(void) { u32 mode; mode = in_le32(JH7110_BOOT_MODE_SELECT_REG) & JH7110_BOOT_MODE_SELECT_MASK; switch (mode) { case 0: return BOOT_DEVICE_SPI; case 1: return BOOT_DEVICE_MMC2; case 2: return BOOT_DEVICE_MMC1; case 3: return BOOT_DEVICE_UART; default: debug("Unsupported boot device 0x%x.\n", mode); return BOOT_DEVICE_NONE; } } void board_init_f(ulong dummy) { int ret; ret = spl_early_init(); if (ret) panic("spl_early_init() failed: %d\n", ret); riscv_cpu_setup(); preloader_console_init(); /* Set the parent clock of cpu_root clock to pll0, * it must be initialized here */ clrsetbits_le32(JH7110_SYS_CRG + JH7110_CLK_CPU_ROOT_OFFSET, JH7110_CLK_CPU_ROOT_MASK, BIT(JH7110_CLK_CPU_ROOT_SHIFT)); ret = spl_board_init_f(); if (ret) { debug("spl_board_init_f init failed: %d\n", ret); return; } } #if CONFIG_IS_ENABLED(SPL_LOAD_FIT) int board_fit_config_name_match(const char *name) { /* boot using first FIT config */ return 0; } #endif |