Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 | /* * (C) Copyright 2003 * Josef Baumgartner <josef.baumgartner@telex.de> * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ #include <common.h> #include <watchdog.h> #ifdef CONFIG_M5272 #include <asm/m5272.h> #include <asm/immap_5272.h> #endif #ifdef CONFIG_M5282 #include <asm/m5282.h> #include <asm/immap_5282.h> #endif #ifdef CONFIG_M5272 /* * Breath some life into the CPU... * * Set up the memory map, * initialize a bunch of registers, * initialize the UPM's */ void cpu_init_f (void) { /* if we come from RAM we assume the CPU is * already initialized. */ #ifndef CONFIG_MONITOR_IS_IN_RAM volatile immap_t *regp = (immap_t *)CFG_MBAR; volatile unsigned char *mbar; mbar = (volatile unsigned char *) CFG_MBAR; regp->sysctrl_reg.sc_scr = CFG_SCR; regp->sysctrl_reg.sc_spr = CFG_SPR; /* Setup Ports: */ regp->gpio_reg.gpio_pacnt = CFG_PACNT; regp->gpio_reg.gpio_paddr = CFG_PADDR; regp->gpio_reg.gpio_padat = CFG_PADAT; regp->gpio_reg.gpio_pbcnt = CFG_PBCNT; regp->gpio_reg.gpio_pbddr = CFG_PBDDR; regp->gpio_reg.gpio_pbdat = CFG_PBDAT; regp->gpio_reg.gpio_pdcnt = CFG_PDCNT; /* Memory Controller: */ regp->csctrl_reg.cs_br0 = CFG_BR0_PRELIM; regp->csctrl_reg.cs_or0 = CFG_OR0_PRELIM; #if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM)) regp->csctrl_reg.cs_br1 = CFG_BR1_PRELIM; regp->csctrl_reg.cs_or1 = CFG_OR1_PRELIM; #endif #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) regp->csctrl_reg.cs_br2 = CFG_BR2_PRELIM; regp->csctrl_reg.cs_or2 = CFG_OR2_PRELIM; #endif #if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM) regp->csctrl_reg.cs_br3 = CFG_BR3_PRELIM; regp->csctrl_reg.cs_or3 = CFG_OR3_PRELIM; #endif #if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM) regp->csctrl_reg.cs_br4 = CFG_BR4_PRELIM; regp->csctrl_reg.cs_or4 = CFG_OR4_PRELIM; #endif #if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM) regp->csctrl_reg.cs_br5 = CFG_BR5_PRELIM; regp->csctrl_reg.cs_or5 = CFG_OR5_PRELIM; #endif #if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM) regp->csctrl_reg.cs_br6 = CFG_BR6_PRELIM; regp->csctrl_reg.cs_or6 = CFG_OR6_PRELIM; #endif #if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM) regp->csctrl_reg.cs_br7 = CFG_BR7_PRELIM; regp->csctrl_reg.cs_or7 = CFG_OR7_PRELIM; #endif #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ /* enable instruction cache now */ icache_enable(); } /* * initialize higher level parts of CPU like timers */ int cpu_init_r (void) { return (0); } #endif /* #ifdef CONFIG_M5272 */ #ifdef CONFIG_M5282 /* * Breath some life into the CPU... * * Set up the memory map, * initialize a bunch of registers, * initialize the UPM's */ void cpu_init_f (void) { } /* * initialize higher level parts of CPU like timers */ int cpu_init_r (void) { return (0); } #endif |